N. Wichmann

Comparison Between the Dynamic Performance of Double- and Single-Gate AlInAs/InGaAs HEMTs

The static and dynamic behavior of InAlAs/InGaAs double-gate high-electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2-D Monte Carlo simulator. The model allows us to satisfactorily reproduce the experimental performance of this novel device and to go deeply into its physical behavior. A complete comparison between DG and similar standard HEMTs has been performed, and devices with different gate lengths have been analyzed in order to check the attenuation of short-channel effects expected in the DG-structures. We have confirmed that, for very small gate lengths, short-channel effects are less significant in the DG-HEMTs, leading to a better intrinsic dynamic performance. Moreover, the higher values of the transconductance over drain conductance ratio gm /gd, and, especially, the lower gate resistance Rg also provide a significant improvement of the extrinsic fmax.

InAlAs-InGaAs double-gate HEMTs on transferred substrate

We report the fabrication and the dc characterization of the first In/sub 0.52/Al/sub 0.48/As-In/sub 0.53/Ga/sub 0.47/As long double-gate (DG) high-electron mobility transistors (HEMTs). These devices have been obtained using a transferred substrate technique. Although the layer structure has not been optimized, a maximum extrinsic transconductance gm of 450 mS/mm is obtained. At the same bias voltage, the drain current I/sub d/ is 120 mA/mm, which gives a large ratio gm/I/sub d/ of 3.8 V/sup -/, indicating the improvement of the charge control efficiency due to the DG structure.

100nm InAlAs/InGaAs double-gate HEMT using transferred substrate

100nm T-gates InP double-gate HEMTs (DG-HEMT) have been fabricated by use of transferred substrate technique. Theses devices are compared with standard single 100nm T-gate HEMT. The maximum extrinsic transconductance gm of DG-HEMT is two times higher than the HEMT one, and the extrinsic output conductance gd is significantly reduced with DG-HEMT. The combined high gm and low gd induced an extremely high intrinsic unloaded voltage gain gm/gd of 100. So, theses results allowed an improvement of the maximum oscillation frequency (f/sub max/) of 30% compared with standard single 100nm T-gate HEMT. These results are attributed to reduction of short channel effects, related to higher charge control efficiency and suppression of buffer effect.

Comparison Between the Noise Performance of Double- and Single-Gate InP-Based HEMTs

The noise performance of InAlAs/InGaAs double-gate (DG) and standard high-electron-mobility transistors (HEMTs) is analyzed by means of an ensemble 2-D Monte Carlo simulator. The DG-HEMT is found to have a better noise behavior than the single-gate (SG) device. The results show a moderate decrease of the and noise parameters for the DG HEMT with respect to that of the SG device, since current fluctuations due to electrons injected into the buffer are eliminated. Moreover, the DG HEMT reveals a significantly lower extrinsic minimum noise figure and a higher associated gain , not only due to the better intrinsic performance but also to the lower contact resistances.

Fabrication and characterization of 100-nm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As double-gate HEMTs with two separate gate controls

In this letter, we demonstrate successful operation of 100-nm T-gates double-gate high electron mobility transistors with two separate gate controls (V/sub g1s/ /spl ne/ V/sub g2s/). These devices are fabricated by means of adhesive bonding technique using enzocyclocbutene polymer. The additional gate enables the variation of the threshold voltage V/sub th/ in a wide range from -0.68 to -0.12V while keeping high cutoff frequency f/sub t/ of about 170 GHz and high maximum oscillation frequency f/sub max/ of about 200 GHz. These devices are considered as being very effective for millimeter-wave mixing applications and are promising devices for the fabrication of velocity modulation transistor (VMT) (Sakaki et al., 1982).

Monte Carlo Comparison Between InP-Based Double-Gate and Standard HEMTs

The intrinsic static and dynamic performance of InAlAs/InGaAs double-gate high electron mobility transistors (DG-HEMTs) is studied by means of an ensemble 2D Monte Carlo simulator. Our model allows going deeply into the physical behavior of this novel device in comparison with similar standard HEMTs. Different gate lengths are analyzed in order to check the attenuation of short-channel effects expected in the DG-structures. The intrinsic cut-off frequency fc of the DG-HEMTs is found to be similar to that of HEMTs, but the higher values of the figures of merit gm/gd and Cgs/C gd lead to an improvement of fmax

Fabrication and characterization of 200-nm self-aligned In 0.53 Ga 0.47 As MOSFET

In this paper, a 200 nm n-channel inversion-type self-aligned In0.53Ga0.47As MOSFET with a Al2O3 gate oxide deposited by Atomic Layer Deposition (ALD) is demonstrated. Two ion implantation processes using silicon nitride side-wall are performed for the fabrication of the n-type source and drain regions. The 200 nm gate-length MOSFET with a gate oxide thickness of 8 nm features the transconductance of 70 mS/mm and the maximum drain current of 200 mA/mm.

Fabrication and fundamentals of operation of an InAlAs/InGaAs velocity modulation transistor

We report the design, fabrication, and characterization of an InP-based InAlAs/InGaAs velocity modulation transistor (VMT) based on the double-gate high electron mobility transistor topology. When electrons are transferred between two channels with different mobility, the drain current is modulated while keeping the total carrier density constant. For the fabrication of the transistor, the epitaxial growth has been optimized in order to accomplish the maximum mobility difference between the two active channels. DC characteristics of our VMT have been extracted and an ensemble Monte Carlo simulator is employed to study the microscopic behavior of the fabricated device. The numerical analysis of the carrier density and velocity variation with the gate bias in differential mode demonstrates the actual velocity modulation operation of the fabricated transistors.

Monte Carlo model for the analysis and development of III-V Tunnel-FETs and Impact Ionization-MOSFETs

Impact-ionization metal-oxide-semiconductor FETs (I-MOSFETs) are in competition with tunnel FETs (TFETs) in order to achieve the best behaviour for low power logic circuits. Concretely, III-V I-MOSFETs are being explored as promising devices due to the proper reliability, since the impact ionization events happen away from the gate oxide, and the high cutoff frequency, due to high electron mobility. To facilitate the design process from the physical point of view, a Monte Carlo (MC) model which includes both impact ionization and band-to-band tunnel is presented. Two ungated InGaAs and InAlAs/InGaAs 100 nm PIN diodes have been simulated. In both devices, the tunnel processes are more frequent than impact ionizations, so that they are found to be appropriate for TFET structures and not for I- MOSFETs. According to our simulations, other narrow bandgap candidates for the III-V heterostructure, such as InAs or GaSb, and/or PININ structures must be considered for a correct I-MOSFET design.

Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy

In this paper we report on the fabrication and electrical characterization of InAs-on-nothing metal-oxide-semiconductor field-effect transistor composed of a suspended InAs channel and raised InAs n+xa0contacts. This architecture is obtained using 3D selective and localized molecular beam epitaxy on a lattice mismatched InP substrate. The suspended InAs channel and InAs n+xa0contacts feature a reproducible and uniform shape with well-defined 3D sidewalls. Devices with 1 μm gate length present a saturation drain current (I Dsat) of 300 mA mm-1 at V DSxa0=xa00.8 V and a trans-conductance (GM ) of 120 mS mm-1 at V DSxa0=xa00.5 V. In terms of electrostatic control, the devices display a minimal subthreshold swing of 110 mV dec-1 at V DSxa0=xa00.5 V and a small drain induced barrier lowering of 50 mV V-1.