Ramalingam Sridhar

Postal address block location in real time

The CEDAR real-time address block location system, which determines candidates for the location of the destination address from a scanned mail piece image, is described. For each candidate destination address block (DAB), the address block location (ABL) system determines the line segmentation, global orientation, block skew, an indication of whether the address appears to be handwritten or machine printed, and a value indicating the degree of confidence that the block actually contains the destination address. With 20-MHz Sparc processors, the average time per mail piece for the combined hardware and software system components is 0.210 seconds. The system located 89.0% of the addresses as the top choice. Recent developments in the system include the use of a top-down segmentation tool, address syntax analysis using only connected component data, and improvements to the segmentation refinement routines. This has increased top choice performance to 91.4%.<<ETX>>

A cross-layer based intrusion detection approach for wireless ad hoc networks

Wireless ad-hoc networks are vulnerable to various kinds of security threats and attacks due to relative ease of access to wireless medium and lack of a centralized infrastructure. In this paper, we seek to detect and mitigate the denial of service (DoS) attacks that prevent authorized users from gaining access to the networks. These attacks affect the service availability and connectivity of the wireless networks and hence reduce the network performance. To this end, we propose a novel cross-layer based intrusion detection system (CIDS) to identify the malicious node(s). Exploiting the information available across different layers of the protocol stack by triggering multiple levels of detection, enhances the accuracy of detection. We validate our design through simulations and also demonstrate lower occurrence of false positives

A special-purpose content addressable memory chip for real-time image processing

An application specific integrated circuit (ASIC) using a special-purpose content addressable memory that performs parallel search and multiple update (PSMU) operation is presented. This chip, referred to as multiple update content addressable memory (MUCAM), can search 256, 8-b-wide locations in parallel for target data and update all such locations with new data within 50 ns. MUCAM has been developed for image component labeling and merging operation in a connected component analyzer. It was fabricated using 0.9- mu m CMOS technology. >

A Cross-layer Approach to Detect Jamming Attacks in Wireless Ad hoc Networks

Building an efficient intrusion detection system (IDS) is a challenging task in wireless ad hoc networks due to the resource constraints and lack of a centralized control. In this work, we present a decentralized monitor-based IDS for detecting jamming type denial of service (DoS) attacks at the lower layers of the protocol stack. The varying channel and network dynamics in ad hoc networks can impair service similar to a jamming scenario, resulting in false positives on intrusion detections. To this end, we incorporate a cross-layer design in our IDS to differentiate the malicious jamming behavior from genuine network failures. We validate our design through simulation, and establish the effectiveness of the model. From the simulation results, we observe a significant improvement in the accuracy of detection and lower false positives

An active intelligent decision support system—architecture and simulation

Abstract Development and implementation of decision support systems to support intelligent decision making is an area of research that has gained in importance in recent years. Due to the increased complexity of decision making, active involvement of the user and the computer in an intelligent way is necessary in the decision process. This paper presents issues in the design of an active intelligent decision support system (IDSS), develops an architectural model based on cooperative distributed problem solving, and performs a simulation of the system using object oriented programming for an example application in airfleet control.

A low-swing differential signalling scheme for on-chip global interconnects

The dense very deep submicron (VDSM) system on chips (SoC) face a serious limitation in performance due to reverse scaling of global interconnects. Interconnection techniques which decrease delay, delay variation and ensure signal integrity, play an important role in the growth of the semiconductor industry into future generations. Current-mode low-swing interconnection techniques provide an attractive alternative to conventional full-swing voltage mode signaling in terms of delay, power and noise immunity. In this paper, we present a new current-mode low-swing interconnection technique which reduces the delay and delay variations in global interconnects. Extensive simulations for performance of our circuit under crosstalk, supply voltage, process and temperature variations were performed. The results indicate significant savings in power, reduction in delay and increase in noise immunity compared to other techniques.

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address single even upsets (SEUs). Robust combinational logic designs capable of tolerating single event transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET mitigation scheme for flip-flops based on the time redundancy principle. The incurred area overhead due to the radiation hardening is minimized by reusing existing components (uses existing scan portion for SET tolerance). As shown by the simulation results, the proposed SET tolerant flip-flop has no performance overheads and simulation results that show the area overheads in ISCAS benchmark circuits are also presented

Intrusion detection in RFID systems

In recent years, advances in radio frequency identification (RFID) technology has led to their widespread adoption in diverse applications such as object identification, access authorization, environmental monitoring and supply chain management. Although the increased proliferation of tags enables new applications, they also raise many unique and potentially serious security and privacy concerns. Security solutions in RFID systems need to be strengthened to ensure information integrity and to prevent hackers from exploiting the sensitive tag data. In this paper, we address the importance of intrusion detection security paradigm for RFID systems. We present an overview of state of the art in RFID security and investigate the limitations of traditional security solutions based on cryptographic primitives and protocols. We propose an RFID intrusion detection model that integrates information from RFID reader layer and middleware layer to detect anomalous behavior in the network, thus improving their resilience to security attacks.

A robust header compression technique for wireless Ad hoc networks

Due to the limited bandwidth of the wireless links in ad hoc networks, compressing the packet headers is an attractive method for efficient usage of the frequency spectrum and for performance enhancement. The objective of this work is to demonstrate the use of a novel end-to-end header compression technique for multi-hop wireless ad hoc networks. Our preliminary analysis shows a significant performance improvement when the proposed Routing-Assisted Header Compression (RAHC) technique is implemented in conjunction with conventional on-demand routing techniques for ad hoc networks.

Impact of Variability on Clock Skew in H-tree Clock Networks

Clock distribution networks play a key role in determining overall system performance. In this paper, the authors investigate the effect of parameter variations on the performance of a commonly used clock distribution structure, a H-tree clock network. The design of robust high performance clock networks face significant challenges due to increasing parameter variations in sub-65nm technologies. As shown in the results, the contribution of interconnect variations to clock skew has risen by upto 3 times from 180nm to 45nm technology. It also suggests that the effect of variability is most prominent at the second and third stages of the 5-stage H-tree clock network. This analysis will help develop mitigation techniques that focus on addressing specific failure mechanisms caused by variability in clock networks