Nabihah Ahmad

Design of AES S-box using combinational logic optimization

Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The architecture employs a Boolean simplification of the truth table of the logic function with the aim of reducing the delay. The S-Box is designed using basic gates such as AND gate, NOT gate, OR gate and multiplexer. Theoretically, the design reduces the overall delay and efficiently for applications with high-speed performance. This approach is suitable for FPGA implementation in term of gate area. The hardware, total area and delay are presented.

A new design of XOR-XNOR gates for low power application

XOR and XNOR gate plays an important role in digital systems including arithmetic and encryption circuits. This paper proposes a combination of XOR-XNOR gate using 6-transistors for low power applications. Comparison between a best existing XOR-XNOR have been done by simulating the proposed and other design using 65nm CMOS technology in Cadence environment. The simulation results demonstrate the delay, power consumption and power-delay product (PDP) at different supply voltages ranging from 0.6V to 1.2V. The results show that the proposed design has lower power dissipation and has a full voltage swing.

AES Cardless Automatic Teller Machine (ATM) Biometric Security System Design Using FPGA Implementation

Automated Teller Machine (ATM) is an electronic banking outlet that allows bank customers to complete a banking transactions without the aid of any bank official or teller. Several problems are associated with the use of ATM card such card cloning, card damaging, card expiring, cast skimming, cost of issuance and maintenance and accessing customer account by third parties. The aim of this project is to give a freedom to the user by changing the card to biometric security system to access the bank account using Advanced Encryption Standard (AES) algorithm. The project is implemented using Field Programmable Gate Array (FPGA) DE2-115 board with Cyclone IV device, fingerprint scanner, and Multi-Touch Liquid Crystal Display (LCD) Second Edition (MTL2) using Very High Speed Integrated Circuit Hardware (VHSIC) Description Language (VHDL). This project used 128-bits AES for recommend the device with the throughput around 19.016Gbps and utilized around 520 slices. This design offers a secure banking transaction with a low rea and high performance and very suited for restricted space environments for small amounts of RAM or ROM where either encryption or decryption is performed.

Advanced Encryption Standard with Galois Counter Mode using Field Programmable Gate Array.

Nowadays, the protection of transferring data is important to prevent the data hack easily. Advanced Encryption Standard with Galois Counter Mode (AES-GCM) plays an important role to provide high assurance of authenticity and data confidentiality in electronics, computers and other communication applications. This paper presents the implementation of AES-GCM by using Field Programmable Gate Array (FPGA) and AES-GCM designs in parallel-pipelined to achieve high performance in term of throughput and latency. The implementation of AES-GCM in FPGA by using 128-bit of input data block, Initialization vector (IV) and Additional Authenticated Data (AAD) to provide a high speed of authenticated encryption / decryption. The key length of AES-GCM is 256-bit to provide the high security system and the operation of key expand designed in parallel to optimize operation time of AES-GCM. The proposed architecture is designed in Verilog hardware description language (HDL) and implemented using DE1-SoC with Cyclone V device. A parallel-pipelined of AES-GCM is introduced and it is operated at 10 MHz, achieved throughput of 16.84 Gbps, utilized of 11,196 slices. AES-GCM is carried out with the key-length of 256-bit is suitable to perform at high speed of electronic applications in term of security.

Charge Pump and Loop Filter for Low Power PLL Using 130nm CMOS Technology

A tri-state charge pump circuit and second order low pass filter circuit were designed to be used in Phase Lock Loop (PLL) system. The proposed design reduces the non-ideal effects such as a current mismatch and charge sharing. Therefore, it can be minimized by providing an equal value for the two switches UP and DOWN. While the charge pump output determines the output condition of the low pass filter. The proposed design have been simulated by using 130nm Complementary Metal Oxide Semiconductor (CMOS) technology in Cadence Tools. The simulation also includes the parameters for tri-state charge pump and second order low pass filter using voltage supply of 1.2 V. The power consumption of the design is 2.07 mW with the output voltage swing from 288 mV to 413.8 mV. The frequency achieved from the proposed design is 4.7 GHz. The total area of the layout that have been measured is 31.4 µm x 22.6 µm (0.7096 mm2). Thus, the proposed design able to achieve the scope of low power consumption and high frequency in smaller technology.

Cyclic Voltammetry Measurement for Cu2O Based Homostructure Thin Film

This experiment is about fabrication of homojunction Copper Oxide (Cu2O) thin film by using electrodeposition method. The p-n homojunction Cu2O was successfully prepared by consecutively depositing p-type Cu2O layer on n-type Cu2O layer by using copper acetate based solution through potentiostatic electrodeposition. At first, the n-type Cu2O was fabricated at pH 6.2 and 6.5 with fixed potential of -0.125V vs Ag/AgCl and time deposition at 30 minutes. Cyclic voltammetry (CV) measurement was carried out on this sample to determine the ideal potential range for fabrication of p-type Cu2O on n-type Cu2O/FTO substrate. From the result, deposition potential of -0.35V and -0.4V vs Ag/AgCl were appropriated for p-type Cu2O thin film fabrication. These potential values were variable with the selected pH values of 12.0 and 12.5 to fabricate the p-type Cu2O thin film. The other parameters such as deposition time fixed at 2 hours bath temperature was set up at 60°C. It was found that the optimum potential deposition was -0.4V vs Ag/AgCl and pH value appropriate for homostructure Cu2O thin film was pH 12.5. Morphological, structural, optical and conductivity characterization of p-n homojunction Cu2O thin film was characterized using Field Emission Scanning Electron Microscopy, X-Ray Diffractometer, Ultraviolet-Visible Spectroscopy and Photoelectrochemical (PEC) cells, respectively.

Hydrophobic rutile phase TiO2 nanostructure and its properties for self-cleaning application

The nanostructured hydrophobic rutile phase titanium dioxide TiO2 and its properties for self-cleaning application were directly synthesized from titanium butoxide (TBOT) precursor deposited on the fluorine doped tin oxide (FTO) substrate through the hydrothermal treatment with different volume of TBOT and adding of Cetyl Trimethylammonium Bromide (CTAB). The samples were characterized respectively by way of field-emission scanning electron microscopy (FE-SEM), water contact angle measurement and Raman spectroscopy for surface analysis system. The FE-SEM results revealed a layer of nanoparticles were growth on the FTO substrate. The surface properties of the samples were studied with a water contact angle measurement. The water contact angle measurement results revealed the hydrophobic of samples as the angle of water droplet on the sample increased. The rutile phase and surface of TiO2 were confirmed using a Raman spectroscopy.The nanostructured hydrophobic rutile phase titanium dioxide TiO2 and its properties for self-cleaning application were directly synthesized from titanium butoxide (TBOT) precursor deposited on the fluorine doped tin oxide (FTO) substrate through the hydrothermal treatment with different volume of TBOT and adding of Cetyl Trimethylammonium Bromide (CTAB). The samples were characterized respectively by way of field-emission scanning electron microscopy (FE-SEM), water contact angle measurement and Raman spectroscopy for surface analysis system. The FE-SEM results revealed a layer of nanoparticles were growth on the FTO substrate. The surface properties of the samples were studied with a water contact angle measurement. The water contact angle measurement results revealed the hydrophobic of samples as the angle of water droplet on the sample increased. The rutile phase and surface of TiO2 were confirmed using a Raman spectroscopy.

Fabrication of TiO2 nanostructures on porous silicon for thermoelectric application

Nowadays, technology is moving by leaps and bounds over the last several decades. This has created new opportunities and challenge in the research fields. In this study, the experiment is about to investigate the potential of Titanium Dioxide (TiO2) nanostructures that have been growth onto a layer of porous silicon (pSi) for their thermoelectric application. Basically, it is divided into two parts, which is the preparation of the porous silicon (pSi) substrate by electrochemical-etching process and the growth of the Titanium Dioxide (TiO2) nanostructures by hydrothermal method. This sample have been characterize by Field Emission Scanning Electron Microscopy (FESEM) to visualize the morphology of the TiO2 nanostructures area that formed onto the porous silicon (pSi) substrate. Besides, the sample is also used to visualize their cross-section images under the FESEM microscopy. Next, the sample is characterized by the X-Ray Diffraction (XRD) machine. The XRD machine is used to get the information about the...

Performance comparison between silicon solar panel and dye-sensitized solar panel in Malaysia

In carrying out experimental research in performance between silicon solar panel and dye-sensitive solar panel, we have been developing a device and a system. This system has been developed consisting of controllers, hardware and software. This system is capable to get most of the input sources. If only need to change the main circuit and coding for a different source input value. This device is able to get the ambient temperature, surface temperature, surrounding humidity, voltage with load, current with load, voltage without load and current without load and save the data into external memory. This device is able to withstand the heat and rain as it was fabricated in a waterproof box. This experiment was conducted to examine the performance of both the solar panels which are capable to maintain their stability and performance. A conclusion based on data populated, the distribution of data for dye-sensitized solar panel is much better than silicon solar panel as dye-sensitized solar panel is very sensitive to heat and not depend only on midday where is that is the maximum ambient temperature for both solar panel as silicon solar panel only can give maximum and high output only when midday.In carrying out experimental research in performance between silicon solar panel and dye-sensitive solar panel, we have been developing a device and a system. This system has been developed consisting of controllers, hardware and software. This system is capable to get most of the input sources. If only need to change the main circuit and coding for a different source input value. This device is able to get the ambient temperature, surface temperature, surrounding humidity, voltage with load, current with load, voltage without load and current without load and save the data into external memory. This device is able to withstand the heat and rain as it was fabricated in a waterproof box. This experiment was conducted to examine the performance of both the solar panels which are capable to maintain their stability and performance. A conclusion based on data populated, the distribution of data for dye-sensitized solar panel is much better than silicon solar panel as dye-sensitized solar panel is very sensiti...