Nabil I. Khachab

A nonlinear CMOS analog cell for VLSI signal and information processing

A simple reconfigurable continuous-time nonlinear CMOS building block for analog VLSI applications is presented. The new block is introduced as a basic analog cell for the implementation of analog VLSI systems. It simultaneously achieves four-quadrant multiplication and division. Its applications in both analog signal and information processing are discussed. These include multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-DC conversion, and neural computing. Using the new cell, a MOS VLSI implementation of a feedback/feedforward neural network is developed which achieves the scalar product of two n-tuple vectors by 4(n+1) MOS transistors and one operational amplifier. To verify the versatility of the new cell and its applications, experimental results obtained from a test chip that was fabricated using the MOSIS 2- mu m CMOS process are included. >

An analog MOS implementation of the synaptic weights for feedback neural nets

The authors introduce a MOS-based realization of the synaptic weight problem for neural nets. The realization is achieved via an adaptation of continuous-time analog multipliers where the weights are assigned as positive or negative voltage levels. The neural network is then realized by double inverters interconnected through the introduced analog multipliers. Using only a single operational amplifier, each analog multiplier is capable of realizing the scalar product Sigma T/sub ij/V/sub j/, j=1, . . ., n, and i is fixed, where V/sub j/; is the output neuron and T/sub ij/ is the assigned positive or negative weight. The authors demonstrate the functionality of the feedback neural networks with MOS-based multipliers using a two-neuron example.<<ETX>>

Configurable CMOS multiplier/divider circuits for analog VLSI

The design of five simple CMOS opamp based multipler/divider circuits is presented. Each two opamp and six MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims.

A new continuous-time MOS implementation of feedback neural networks

An economical, simple, and versatile MOS cell that lends itself to the MOS implementation of feedback/feedforward neural networks is introduced. The new cell achieves vector scalar product of the form Sigma T/sub ij/V/sub j/, where y=1 . . ., n, i is fixed, V/sub j/ is the output of neuron i, and T/sub ij/ is the assigned positive or negative weight that is realized through voltage levels. The new circuit comprises only one operational amplifier (op-amp) and two input MOS depletion transistors. The vector scalar product of 2 n-tuple vector inputs is achieved by using 2(n+1) MOS transistors. This offers an economical alternative for VLSI analog neural networks. The analog neural network is realized by interconnecting double inverters through the new vector scalar product circuits. Moreover, the output voltage is tunable via programmable DC control voltages. The technique is demonstrated with an example of a two neuron circuit.<<ETX>>

Current-mode neural network building blocks for analog MOS VLSI

An initial design of a continuous-time version of a decision directed filter, which uses a compact neural hardware structure, is presented. Synaptic weight storage and nonvolatile floating-gate storage are discussed. Current mode, neural network building blocks are described.<<ETX>>

Fourth order filter structures using Operational Trans-resistance Amplifiers

In this paper, we present the design of fourth order filter structures by using the Operational Transresistance Amplifiers (OTRA). In this paper OTRA based second order low pass and high pass filter is verified and fourth order band pass and notch filter topologies are also obtained. The resulting filters are simulated by 0.18μm CMOS process through Orcad Unison Suite. The results of these filters are discussed and compared in terms of performance and frequency range.

A BiCMOS cell with applications to highly linear analog transconductor realizations

A basic six-transistor cell comprising of a MOST input and tuning stage, in addition to a bipolar current mirror and source stage has been presented. This overall BiCMOS setup functions with high linearity at reduced power supplies and has been configured for voltage programmable transconductor applications. Simulation results confirm the high performance operation of the proposed Voltage to Current Converters (VICs).

A simple all MOS continuous-time multiplier/divider cell and its applications in VLSI signal processing

A novel, simple, all-MOS continuous-time multiplier/divider parameterized cell is presented. The cell uses only four MOS depletion FETs and two operational amplifiers (op-amps) or one fully balanced output op-amp. The resulting circuit is fully integrable in MOS technology. The cell is highly reconfigurable, versatile, extremely simple to design, and its output is conveniently programmed via DC control voltages. Some of the applications of the cell in analog VLSI signal processing include analog multiplication, signal squaring, division, signal inversion, amplitude modulation, RMS-to-DC conversion, and sensor linearization. Moreover, the new circuit is easily extendible to achieve analog vector multiplication, and hence lends itself naturally to the analog MOS VLSI implementation of feedback/feedforward neural networks.<<ETX>>

A new technique for the implementation of programmable-Q MOSFET-C filters

A new technique for the implementation of programmable-Q MOSFET-C filters is introduced. The technique uses nonlinear circuits in the feedback path of the filter, allowing the tuning of Q through DC control voltages. The resulting topology is fully compatible with MOS technology. In addition, the center frequency omega /sub 0/ of the filter is also programmable via DC voltage controlled transconductance elements. An interesting connection between programmability, design automation, and physical layout of analog integrated circuits is discussed. The application of this technique to a second-order biquad filter is presented, along with computer simulation results.<<ETX>>

Synchronization of two RCL shunted Josephson Junctions

This paper deals with the synchronization of two identical RCL-shunted Josephson Junctions (RCLSJJs). The RCLSJJ displays chaotic behavior for certain values of the parameters of the circuit. Two control schemes are proposed for the synchronization of two identical RCLSJJs. The proofs of these controllers are based on the Lyapunov theory. The proposed controllers are validated through MATLAB simulation results which indicate that the proposed schemes are very effective in synchronizing two RCLSJJs.