Seyed Ebrahim Esmaeili

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics extracted from layout. The LS-DCCFF enables 6.5% reduction in power compared to the full- swing flip-flop with 19% area overhead. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low-swing sinusoidal clock has been characterized. The LS-DCCFF has 870 ps longer data to output delay as compared to the full-swing flip-flop at the same setup time for a 100 MHz sinusoidal clock. The functionality of the proposed flip-flop was tested and verified by using the LS-DCCFF in a dual-mode multiply and accumulate (MAC) unit fabricated in TSMC 90-nm CMOS technology. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead for the MAC.

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant clock distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant clock networks.

Estimating required driver strength in the resonant clock generator

A detailed analytical approach is proposed to determine the required driver strength in the resonant clock generator. The proposed approach reduces area and power overhead by eliminating the need to have switches with programmable widths and reference pulses with programmable duty cycles. Simulation results show accurate estimation of the required driver strength at short pulse widths. However, as the pulse width increase, accuracy reduces due to overestimation of the transistor driving capability.

Dual-edge triggered energy recovery DCCER flip-flop for low energy applications

Resonant clocking techniques have been shown to achieve significant power reduction compared to square wave clocking. In this paper, we propose a dual-edge triggered Differential Conditional Capturing Energy Recovery (DE-DCCER) flip-flop that allows the clock frequency to be reduced by a factor of two. The proposed flip-flop was tested using STMicroelectronics 90nm process technology. Simulation results show the correct operation of the dual-edge triggered flip-flop at a frequency of 250MHz. Modeling the entire system of the clock distribution network with approximately 10,000 flip-flops shows that dual-edge triggering achieves a 56% power reduction in the clock tree and up to 21% total power reduction for the entire system with a penalty of 36.8% increase in area.

Skew compensation in energy recovery clock distribution networks

In this paper a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. Three types of flip-flops: ¿fast¿, ¿standard¿, and ¿slow¿ are used. Distributing flip-flops according to their delay requirements would reduce the effect of the clocks skew on the outputs of sequentially adjacent flip-flops. This approach increases the skew bounds required by algorithms to balance the skew in the clock distribution network leading to reduced design complexity. Theoretical analysis and simulation results at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% of the clock period can be compensated for.

A novel approach for skew compensation in energy recovery clock distribution networks

In this paper a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. Three types of flip-flops: ?fast?, ?standard?, and ?slow? are used. Distributing flip-flops according to their delay requirements would reduce the effect of the clocks skew on the outputs of sequentially adjacent flip-flops. This approach increases the skew bounds required by algorithms to balance the skew in the clock distribution network leading to reduced design complexity. Theoretical analysis and simulation results at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% of the clock period can be compensated for.

Power reduction in energy recovery and square-wave clock distribution networks operating at half frequency with dual-edge triggered flip-flops

Dual-edge triggered flip-flops allow the operation of the clock distribution network at half the frequency leading to significant power reduction. We have simulated an energy recovery and a square-wave clock distribution network with 10,240 single-and dual-edge triggered flip-flops at 500 MHz and 250 MHz, respectively. Dual-edge triggering results in a total power reduction of 26% in the energy recovery clock. In square-wave clock distribution network, dual-edge triggering results in a total power reduction of 16%.

Integrated Power and Clock Distribution Network

In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a differential power-clock signal (Pwr_Clk) with a suitable dc voltage level and sinusoidal voltage-swing feeds the VDD ports in combinational and sequential elements. A clock buffer is used for sequential elements in order to extract a full-swing clock from the differential Pwr_Clk+ and Pwr_Clk- signals. IPCDN does not require any change to be made to the conventional combinational and sequential circuit design. The proposed elements of IPCDN, including the LC differential Pwr_Clk driver and the clock buffer, have been simulated using Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology with a Pwr_Clk signal, a 1-V dc component, and 400-mV sinusoidal swing at a frequency of 5 GHz. In addition, the behavior of a master-slave flip-flop with IPCDN was investigated at extreme corners. Simulation results demonstrate correct functionality of all elements of the IPCDN. Comparing IPCDN to a buffered square-wave clock distribution network illustrates that, with a heavily loaded network, IPCDN achieves around 20% reduction in power. This percentage increases when the network capacitance is dominating.

Dual-edge triggered pulsed energy recovery flip-flops

Resonant clocking is an emerging effective method for reducing power consumption in the clock distribution network. In this technique a resonant (sinusoidal) clock replaces the traditional square wave clock signal. In this paper we combine the emerging resonant clocking technique with the well known dual-edge triggering scheme to enable further power reduction in the clock tree. We propose dual-edge triggering in three pulsed flip-flops that operate with a sinusoidal clock signal; namely: the Static Differential Energy Recovery (SDER) flip-flop, the Differential Conditional Capturing Energy Recovery (DCCER) flip-flop, and the Single-ended Conditional Capturing Energy Recovery (SCCER) flip-flop. The proposed dual-edge flip-flops were tested using STMicroelectronics 90nm process technology. Simulation results show the correct operation of the dual-edge triggered flip-flop at a frequency of 250MHz with throughput of 500 MHz.

Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity

In this paper, we propose a dual-edge sense amplifier flip-flop (DE-SAFF) using an improved clocking scheme to reduce area, power, and complexity. The proposed scheme does not require any changes on the single-edge flip-flop to enable dual-edge triggering. The extracted circuit layout of the proposed DE-SAFF has been simulated in TSMC 65-nm technology at a frequency of 2.5 GHz and a throughput of 5 GHz. Simulation results show correct functionality of the proposed flip-flop under process, voltage, and temperature (PVT) variations. Comparing the proposed DE-SAFF to other flip-flops, show that in addition to reduced design complexity, the proposed flip-flop has low power consumption and a lower area.