Nadine Azemard

Design and selection of buffers for minimum power-delay product

Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to a standard cell library in comparing implementations for different selection alternatives.

Explicit evaluation of short circuit power dissipation for CMOS logic structures

For supply voltage standards such as Vdd > V TN + |V TP | short-circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short-circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows up the design and load parameters. Validations are performed on different configurations of inverters by comparison with HSPICE simulations. Discussions on the relative importance of short-circuit and dynamic power dissipation is given, together with considerations allowing an easy extension to gates.

Voltage scaling and body biasing methodology for high performance hardwired LDPC

This paper aims at introducing a safe voltage scaling and body biasing methodology for Low-Density Parity Check (LDPC) hard-wired IP. The proposed methodology allows an efficient post-silicon tuning of the LDPC, and the performances can be adapted to High Speed mode, or Low Operating Power mode, or Low Standby Power mode requirements. Concrete 45nm silicon results are introduced in this paper to demonstrate the added value of the methodology. More precisely, it is shown that running the High Performance mode leads to +24% on circuit maximum operating frequency. And the Low Standby Power mode results on x0.73 leakage minimization. The proposed adaptive LDPC encoder/decoder can remove some barriers to the adoption of long LDPC codes on portable devices.

Energy study for 28nm FDSOI technology

Due to the effects of the Moores law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On- Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.

Product on-chip process compensation for low power and yield enhancement

This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.

Design Optimization with Automated Cell Generation

It is well recognized that designs based on automated standard cell flow have been found slower and larger in area than comparable designs manually generated or optimized. On the other hand it becomes necessary for designers to quickly prototype IP blocks in newly available processes. This paper describes an approach combining a performance optimization by path classification (POPS) tool with a transistor level layout synthesis tool (I2P2) dedicated to CMOS synchronous design fast generation. Validations are given on a 0.18 μm CMOS process by comparing standard cell approach to the proposed approach.