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Dive into the research topics where Nagaraju Bussa is active.

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Featured researches published by Nagaraju Bussa.


international conference on consumer electronics | 2007

Lightweight Encryption for Images

Anil Yekkala; Narendranath Udupa; Nagaraju Bussa; C.E.V. Madhavan

Advancements in multimedia commerce resulted in rapid growth in the amount of multimedia data transferred over network. The multimedia data stored on the Web servers as well as the data transferred over the network needs to be protected from piracy and eavesdropping. Hence there is a strong need for encrypting the multimedia content. But owing to the size of the multimedia content, and real time requirements for encoding, transmitting and decoding the multimedia content, usage of standard encryption/decryption schemes prove to be an overhead. Hence lightweight encryption schemes are gaining popularity. The schemes are based on using the structure of the multimedia content, and partially encrypting the content such that it results in insertion of sufficient noise to make the content unintelligible. In this paper we present a scalable lightweight encryption scheme that can be used for encrypting/decrypting image and video, and it uses a simple protocol to identify the portion of the content that has been encrypted.


application-specific systems, architectures, and processors | 2005

Artificial deadlock detection in process networks for ECLIPSE

N. Bharath; S. K. Nandy; Nagaraju Bussa

Kahn process network (KPN) is a popular model of computation for describing streaming applications. In a KPN model, processes communicate through unbounded unidirectional FIFOs. When theoretically unbounded FIFOs are implemented using finite memory, artificial deadlocks can occur due to one or more FIFOs having insufficient sizes. Generally, a system designer must be able to make a design time trade-off between execution time and memory usage, preferably using no more memory than required for obtaining a certain execution time. But it is practically impossible to decide at design time, FIFO sizes that are sufficient to run the application without any artificial deadlocks. Hence, there is a need for runtime mechanism for handling the artificial deadlock situations in process networks. Existing mechanisms detect artificial deadlocks only after all KPN processes block. This results in excessive blocking of processes and an application that appears to hang. In this paper, we present an improved mechanism for early detection of artificial deadlocks and its implementation on ECLIPSE (extended CPU local irregular processing architecture), an application domain specific architecture.


asia and south pacific design automation conference | 2007

A Run-Time Memory Protection Methodology

Udaya Seshua; Nagaraju Bussa; Bart Vermeulen

In this paper we present a novel methodology to help debug memory corruption errors during application debug. In this methodology an optimal balance between hardware and software instrumentation is chosen to check at run-time all memory accesses made by an application. To achieve this balance a set of benchmark applications is first analyzed to determine their memory access patterns. The analysis results are used to make our approach low-cost both from a software performance penalty and a hardware area point-of-view. Experimental results show that our innovative approach typically requires less than 2% of a CPU in silicon area for a less than 1% run-time performance overhead. Our method is both low-cost and applicable to high performance microprocessors as well as time-constrained embedded systems.


international conference on robot communication and coordination | 2007

Path planning using Shi and Karl level sets

Randeep Singh; Nagaraju Bussa

Path planning for mobile robots is a well researched problem for over three decades. In this paper, we test and evaluate a new approach based on Shi and Karl Level Sets for mobile robot path planning. The evolution speed of these level sets is the fastest available implementation of level sets till date that prompted us to test the algorithm in the path planning domain. Level Sets have the advantage that they can support multiple robots and multiple goals in a single framework. This approach is similar to the Pixel Level Snakes but much faster and the resulting paths are different for some obstacle courses using these two approaches. To keep experiments simple we consider a holonomic point robot moving amidst stationary obstacles. The visual results presented in this paper are preliminary and tested in simulations only.


Archive | 2006

Performance Analysis Based System Level Power Management

Nagaraju Bussa; Harsh Dhand; Balakrishnan Srinivasan


Archive | 2006

Means and method for debugging

Nagaraju Bussa; Narendranath Udupa; Sainath Karlapalem


Archive | 2007

Region protection unit, instruction set and method for protecting a memory region

Hubertus G. H. Vermeulen; Nagaraju Bussa; Udaya Seshua


Archive | 2006

DATA PROCESSING SYSTEM AND METHOD OF TASK SCHEDULING

Narendranath Udupa; Nagaraju Bussa


Archive | 2005

DATA PROCESSING SYSTEM AND METHOD FOR CACHE REPLACEMENT

Sainath Karlapalem; Bijo Thomas; Nagaraju Bussa


Archive | 2011

Processing of periodic physiological signals

Jithendra Vepa; Nagaraju Bussa; Srinivas Rao Kudavelly

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