Abhishek Jain

On-chip delay measurement circuit

A novel On-chip delay measurement circuit is presented which is suitable for wide applications involving on-chip measurements, monitoring and process compensation. The circuit is based upon multiple characterization units consisting of ring oscillator, latches and counter. The delay unit used in ring oscillator defines the measurement resolution for the characterization unit. Each characterization unit has different delay cell with delay varying by few Pico-seconds (~1 to 5 picoseconds) with other one, which helps in increasing the resolution. All units give values based on their delay units and collectively all values forms a statistical space whose median gives the pulse width value. In this way, the circuit overcomes the limitations of earlier proposed on-chip measurement systems by offering high accuracy, high resolution and wide range of measurement using very few components. Silicon results on CMOS 40nm technology node for characterization of memory access time based upon proposed system are also presented.

An on-chip flip-flop characterization circuit

The performance of the sequential digital circuit (Speed, Power consumption etc.) depends upon the performance of flip-flop used in the design. ASIC design flows use characterized data of flip-flops for final signoff. Therefore its critical to know precisely the accuracy of characterized data with respect to the actual behavior of flip-flops on silicon. An on-chip flip-flop characterization circuit (FCC) has been presented here which gives the accurate estimation of various parameters of flip-flop such as CP-Q Delay, Setup time, Hold time and Power consumption. The system consists of a digital controller and characterization circuit which are based upon configurable oscillator which could be programmed to oscillate in different configurations or could be operated in functional mode for functional verification. The delay values are calculated by processing the value of time period of oscillator in different modes. The system was fabricated in 40nm CMOS technology and the flip-flop parameters are extracted from it.

A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder

Following the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV specific standard cells library, the circuit was designed following standard industrial implementation and verification flows. The BCH circuit runs at 0.330V, 600kHz frequency and needs 1.27nJ to decode a 252bits frame. With 14% of extra power compared to typical process, applying forward bias enables to compensate temperature and skewed process effects, regaining 150mV minimum operating voltage.