Nagendra Gajjar

Implementation of edge detection algorithms in real time on FPGA

Edge detection servers as a footstone step in image and video processing. These detected edges can further be given as input to other higher level applications like image enhancement, object recognition, object tracking etc. Literature provides various algorithms for edge detection in various domains. At the same time the process is extremely computational exhaustive. For carrying out this task in real time a system which is really fast is required. Software does not seem to be a suitable candidate for implementing it in real time. We require some technology that has huge amount of parallelism. The high amount of computation power in limited time can be achieved by using FPGA as a platform. Field Programmable Gate Array (FPGA) structures are reconfigurable in nature. These FPGAs can be programmed using a Hardware Description Language. But the popularity of FPGA has increased with the availability of high level tools for configuring it. These tools make the FPGA programming easier. This work proposes a real time embedded solution of various edge detection algorithms like Sobel, Laplacian and Prewitt. The performance evaluation of the proposed work is done on various platforms. The throughput is significantly high with a speedup of 26x-50x and the design time decreasing 5 to 6 times. The real time FPGA solution of edge detection algorithms is designed using a powerful design tool Altium Designer for hardware software co design. A 32-bit soft RISC TSK3000A is integrated as a peripheral to the edge detection hardware. The very same tool is also integrated to the ASP generated by CHC(C to Hardware). This CHC takes an input from DVD player and the processed output is given to VGA monitor. The results are verified in real time with an input video from DVD and an output on the VGA monitor.

Reconfigurable architectures for GNSS receiver

Satellite based navigation is a rapidly growing application of satellite systems. The recent development of the various Global Navigation Satellite Systems (GNSS) demands attention towards very important technical aspects of interoperability and compatibility. Navigation solution from different constellations translates to an improvement in higher measurement redundancy and improved reliability. In the interoperable receivers the most expensive parts — front ends — can be shared for signal reception of different systems. The scope of this paper is to discuss the reconfigurable Software Defined Receiver (SDR) for GNSS. The paper also opens a window to the implementation of reconfigurable hardware/software multioperable GNSS receiver, featuring sufficient computational power and flexibility.

Deep neural network compression via knowledge distillation for embedded applications

Deep neural networks have shown significant success across various applications. To solve the complex problems, the increasing depth and complexity pose the challenges of large computation and storage requirements when deploying such networks on embedded devices with limited storage and power. Many techniques have been developed by researchers to compress the deep neural networks to make them deployable on portable devices by reducing the storage requirements. This paper describes the implementation of deep neural network with teacher student model. A comparatively smaller student model learns the information passed from the larger teacher model without losing the accuracy and its learning/inference rate is also improved. So this kind of framework is suitable for embedded applications deployment where real-time performance is required.