Vijay Savani

Voice conversion algorithm

Recently, a lot of work has been done in the speech technology. The main concentration being on Text-to-speech and automatic speech recognition techniques, voice conversion is yet an undeveloped and naïve field in Speech Technology and a lot of contribution from speech researchers is expected in upcoming days. In this paper an approach for static voice conversion is discussed. Static speech parameters are the parameters over which speaker has least control such as vocal tract structure, natural pitch of speech etc. Here, two main parameters are considered Vocal Tract Structure and Pitch. For conversion process speech is resolved in two components, excitation component and filtered component using a Linear Predictive coding [LPC] based source-filter. The pitch contour is determined by an autocorrelation. The excitation component is generated using a set of signal generators generating the determined pitch and are driven by voicing detection. Filter coefficients are modified to approach target speaker coefficients for voiced segments and for unvoiced segments filter coefficients of source are used straightaway.

Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator

Circuit intricacy, high-speed, low-power, small area requirement, and high resolution are crucial factors for high-speed and low-power applications like analog-to-digital converters (ADCs). The delay analysis of classical dynamic latch comparators is presented to add more insight of their design parameters, which effects the performance parameter. In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and requires smaller die area. The proposed comparator benefits from a new shared charge logic based reset technique to achieve high-speed with low-power consumption. It is shown by simulation and analysis that the delay time is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 90nm CMOS technology. The results show that, for the proposed comparator, the delay is 51.7 ps and consumes only 33.62 W power, at 1V supply voltage and 1GHz clock frequency. In addition, the proposed dynamic latch comparator has a layout size of 7.2m8.1m.