Nam-Seog Kim

Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis

This paper describes the sub-Nyquist rate digital-to-analog conversion technique for a direct waveform synthesis (DWS) transmitter. IEEE 802.22 TV band Cognitive Radio (CR) transmitter requires seamless frequency hoping and wide frequency coverage of 54 MHz-806 MHz. The proposed transmitter directly converts the digital baseband samples to RF frequencies in the target channels obviating the up-conversion mixer. The mostly-digital architecture of this transmitter features agile functionality support for Software Defined Radio (SDR) operation. A 10-bit 600-MS/s multi-mode DAC shapes the analog output spectrum envelope to enhance image spectrum located in the target channels and suppress other unwanted harmonics. Compared to Nyquist rate direct synthesis, this sub-Nyquist rate DWS architecture reduces both system complexity and power consumption by half.

Denoising traffic collision data using Ensemble Empirical Mode Decomposition (EEMD) and its application for constructing Continuous Risk Profile (CRP)

Filtering out the noise in traffic collision data is essential in reducing false positive rates (i.e., requiring safety investigation of sites where it is not needed) and can assist government agencies in better allocating limited resources. Previous studies have demonstrated that denoising traffic collision data is possible when there exists a true known high collision concentration location (HCCL) list to calibrate the parameters of a denoising method. However, such a list is often not readily available in practice. To this end, the present study introduces an innovative approach for denoising traffic collision data using the Ensemble Empirical Mode Decomposition (EEMD) method which is widely used for analyzing nonlinear and nonstationary data. The present study describes how to transform the traffic collision data before the data can be decomposed using the EEMD method to obtain set of Intrinsic Mode Functions (IMFs) and residue. The attributes of the IMFs were then carefully examined to denoise the data and to construct Continuous Risk Profiles (CRPs). The findings from comparing the resulting CRP profiles with CRPs in which the noise was filtered out with two different empirically calibrated weighted moving window lengths are also documented, and the results and recommendations for future research are discussed.

A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio

This paper presents a fully integrated ultra wideband (UWB)-based cognitive radio (CR) transceiver for 1 Gb/s data-rate energy-efficient short-range wireless connectivity by scavenging triple discrete inactive frequency bands in 3.1- 10.6 GHz ISM band. The transceiver including receivers (RXs), transmitters (TXs), spectrum sensors, and synthesizers is implemented in 1 V 65 nm standard CMOS technology. A novel pulse generator (PG) enables the TX to meet UWB emission mask and to reduce spectral sidelobe peak by <;-40 dBc with low power consumption of 3.6 mW. A dual-mode RX front-end provides quadrature analog correlation (QAC) for analog domain matched filtering during communication and analog wavelet-based energy detection (ED) during spectrum sensing (SS) without changing circuitry. The transceiver achieves the minimum energy consumption of 59.7 pJ/b with 1.97 × 10-4 bit error rate (BER) and the maximum energy consumption of 102.3 pJ/b with 1.25 × 10-3 BER. Die area is 4.6 mm2 with on-die phase-locked loops (PLLs) and pads.

A 1Gb/s energy efficient triple-channel UWB-based cognitive radio

A triple-channel BPSK UWB-based cognitive radio provides energy efficient 1Gb/s short-range connectivity by scavenging triple discrete inactive frequency bands in 3.1-10.6GHz ISM bands. The developed transceiver in 65nm CMOS achieves the minimum energy consumption of 59.7pJ/b with 1.97×10-4 BER. Die area is 4.6mm2 with on-die PLLs.

A 3–10mW, 3.1–10.6GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios

An integer-N charge pump QPLL provides 3.168 - 10.56GHz lock range, -108.38dBc/Hz phase noise at 1MHz offset, and -59.42dBc reference spur with digital calibration technique for charge pump mismatch while consuming 10.1mW at 10.56GHz with 4-divder at the output. A wideband low power TSPC programmable divider supports 57 sub-bands. It is implemented in a 1V 65nm CMOS process. Active area is 0.12mm2.

A 0.2 to 1.7 GHz low-jitter integer-N QPLL for power efficient direct digital RF modulator

A wide lock-range supply regulated integer-N QPLL is proposed to reduce power consumption of the wideband direct digital RF modulator. SINC roll-off characteristic for supply noise of the inverter-based ring-VCOs in frequency domain maximizes loop bandwidth of the wide lock-range PLL. The proposed charge pump keeps loop bandwidth for all integer-N divider ratio. The fabricated QPLL achieves 0.2 to 1.7GHz lock rage with 10MHz bandwidth, 100MHz reference, and on-chip loop filter. The RMS jitter is 1.28ps, maximum supply noise sensitivity is 0.34rad/V, and power consumption is 13.2mW from 1V supply at 1.7GHz PLL output frequency. The active area is 0.064mm2.

A 3.1-10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers.

A triple-channel wavelet-based dual-resolution spectrum sensor fabricated with 1V 65nm CMOS technology provides 3.1-10.6GHz range of spectrum sensing bandwidth with <;6.4mW/GHz efficiency. Dual-resolution cooperative sensing with two adjacent channels eliminates fine detection process, which leads to <;0.4msec of total sensing time. The spectrum sensor achieves the minimum detection sensitivity of -75dBm and out of band rejection of <;-45dBc by exploiting triangular wavelet with LPF. 3.1-5GHz harmonic rejection mixers suppress third harmonic to -32dBc. Die area is 2.75mm2 with on-die PLLs.