Nam Sung Woo

A heuristic method for FPGA technology mapping based on the edge visibility

We present an efficient technology mapping method for lookup table-based FPGA architectures. We first introduce lhc notion of edge visibility. Wc then formulate lhc problem of finding the area-optimal technology mapping as a problem of assigning visibility values to edges of input Boolean network to minimize the number of nodes in the network. We describe an algorithm that assigns visibility valtrcs efficiently. We compare our method to the “xl_cover” algorithm provi(ied by the MIS-pga systcm.

Codesign from cospecification

Describes an object-oriented codesign specification approach designed to eliminate the bias introduced from using more commonplace software or hardware specification languages. The goal is to investigate automated partitioning of behavior into hardware and software. The design methodology allows gradual, continuous repartitioning of codesign operations during design. For instance, designers might start with an all-software implementation and check the implementations functionality: they might then refine the implementation over time to a mixed hardware-software implementation. At the system level, the authors use an object-oriented approach to identify the basic objects and associated functions of a system. They divide them into three groups: hardware, software, and codesign . They represent the codesign groups objects and functions using a prototype codesign specification language, Object-Oriented Functional Specifications (OOFS), which lets one describe system state in objects and write object methods as pure functions. Thus, the authors can describe complex systems without biasing the implementation toward hardware or software.<<ETX>>

Postlayout logic restructuring using alternative wires

In this paper, we propose a layout-driven synthesis approach for field programmable gate arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuits functionality. Allowing the logic blocks to have alternative functions also increases the chance of successful routing. A redundancy addition and removal technique is used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

Layout Driven Logic Synthesis for FPGAs

In this paper, we propose a layout driven synthesis approach for Field Programmable Gate Arrays (FPGAs). The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA. The alternative wires (in the logic level) that can be routed through less congested areas substitute the unroutable wires without changing the circuits functionality. Allowing the logic blocks to have alternative functions also increases the flexibility of routing. The redundancy addition and removal techniques are used to identify such alternative wires. Experimental results are presented to demonstrate the usefulness of this approach. For a set of randomly selected benchmark circuits, on the average, 30%-50% of wires have alternative wires. These results indicate that the routing flexibility can be substantially increased by considering these alternative wires. Our prototype system successfully completed the routing for two AT&T designs that cannot be handled by an FPGA router alone. The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.

An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.

We developed a new method, called MP2, for partitioning networks into multiple (> 2) blocks each of which has both size and pin constraints. The MP2 method uses an improvement approach and tries to minimize the total number of terminals of all blocks while satisfying the pin and size constraints of every block. It supports multiple classes of cells in input networks and blocks. It makes use of a scalar value of benefit which captures lookahead information. It is the first improvement method that considers pin constraints of blocks. It has been applied to partitioning technology-mapped circuits into multiple FPGA chips. In addition to describing the MP2 method, we will discuss some interesting findings we gleaned during our experiments.

A global, dynamic register allocation and binding for a data path synthesis system

We developed a new algorithm for efficient register allocation and binding used in data path synthesis. Our algorithm determines both the number of registers and the mapping from variables to registers simultaneously during data path allocation so that the cost, i.e., area, of the registers and connections to/from the registers can be minimized. The algorithm selects the “best” register for each input and/or output variable of operations. This register allocation/binding algorithm is used with a data path allocation algorithm that exploits trade-off among all kinds of hardware elements. We present experimental results of our algorithm.

A cost function based optimization technique for scheduling in data path synthesis

A combinatorial optimization technique has been developed and applied to the scheduling problem in data path synthesis. The cost function is minimized using a gradient-like method, and constraints are satisfied by a new technique analogous to the combination of the penalty method and the feasible direction method used for nonlinear optimization. To overcome the drawbacks of assigning operations to control steps one at a time, this technique assigns all the operations to control steps simultaneously. Experimental results show that this method is as good as or better than other published methods.<<ETX>>

The benefits of flexibility in lookup table-based FPGAs

FPGAs (field programmable gate arrays) need not be limited to a single fixed-size truth table in each block. The authors discuss the utility of allowing each blocks single large table (e.g. one 5-input, 32-b table) to be reconfigured into smaller tables (e.g. eight 4-b tables). Results describing the efficiency of packing some standard benchmark circuits into various configurations are presented and the cost/benefits discussed. It is shown that a logic block containing four lookup tables, each of which is 8-b RAM, is the best choice if only the area efficiency is considered. It is also shown that if circuit speed is considered, a logic block containing two lookup tables, each of which contains 16 b of RAM, is the best choice. >

Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs

This paper shows that cascade circuits in the logic cells of all current lookup table based FPGAs support only linear cascading chain and, as a result, contribute to long cascading delay. We present an enhanced cascade circuit that will reduce cascading delay significantly: from linear time to log time in terms of the number of logic cells cascaded. We show that the additional area for the new cascade circuit is very small. We discuss an interaction between architecture design decision and CAD (in particular, placement) for the design of dedicated routing structure for cascade signals between logic cells. We illustrate the advantage of the new cascade circuit with an example of 32-bit equality checking circuit.

ORCA: A New Architecture for High-Performance FPLs

AT&Ts ORCA (Optimized Reconfigurable Cell Array) architecture extends FPGA applicability into a larger domain than is possible with todays parts, including datapath intensive designs such as memory controllers, signal processing parts, and telecommunication interfaces. Key to the suitability of the ORCA for these jobs is the fact that each of its basic blocks is capable of processing four bits. So, for example, a 16 bit adder requires exactly 4 blocks, not 9 or 16 as in other architectures. Yet the total complexity of each block is comparable to other current parts, thus yielding a significant improvement in functional density.