Dwight D. Hill

Routable technology mapping for LUT FPGAs

A routing-driven technology mapper for lookup-table, (LUT)-based field-programmable gate arrays (FPGAs) is presented. The approach is based on performing mapping aimed at routing feasibility. For an FPGA of given size (number of LUTs), the logic being implemented is distributed in such a manner that the total wire length is minimized and the routing resources are not overutilized. Simulated annealing is used to perform mapping, placement, and global routing in tandem. The algorithm can handle both combinational and sequential logic circuits, and has been implemented for combinational circuits. Experiments on MCNC benchmark circuits show encouraging results.<<ETX>>

Optimized reconfigurable cell array architecture for high-performance field programmable gate arrays

The authors describe the optimized reconfigurable cell array (ORCA) field programmable gate array (FPGA) architecture, which incorporates support for large datapath circuits on a nibble wide basis, without diminishing the support for random logic control applications. This is accomplished by providing a programmable function unit which is equally adapted to both environments. The routing structure is similarly designed to allow nibbles of data to be moved around the chip efficiently, while not penalizing the individual connections that characterize typical control logic. The ORCA FPGA and its associated computer-aided design (CAD) system provide users with the opportunity of implementing datapath circuits as well as control circuits easily and efficiently.

Experiments using automatic physical design techniques for optimizing circuit performance

A system that accepts a transistor level net list, tunes it for high performance, and automatically lays it out is described. The system consists primarily of two components, TILOS and SC2D. The first component, TILOS, adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures are described, and their effect is illustrated with several examples, ranging from a few dozens of transistors to tens of thousands.<<ETX>>

A CAD system for the design of field programmable gate arrays

Field Programmable Gate Arrays (FPGA’s) are a relatively new type of chip. This paper describes the software necessary to support two distinct but closely related aspects of them: the development of a new FPGA architecture, and the use of FPGA’s from an application viewpoint. The basic CAD support structure consists of a set of file formats and programs that successively bind and evaluate design decisions. The FPGA designer starts by specifying a block architecture as a schematic. This is analyzed, manipulated, and condensed into a set of files that characterize the routing capabilities and programming requirements of the proposed FPGA design. The application designer specifies a circuit in a standard format (SLIF). This is bound to the resources available in the generic FPGA. The result is a configuration file that maps the application onto the proposed FPGA fabric. During FPGA development, the efficiency of this mapping can be analyzed, and the architecture modified. Once the FPGA has been fabricated, the configuration data can be sent to the actual hardware.

Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine

Tabula Rasa is a user reconfigurable hardware system under development in AT&T Bell Labs. Its purpose is to assist in the development of new hardware systems, and possibly to serve as a computing engine in its own right. The core of the system is a full-custom CMOS chip. This chip has electrically programmed logic and routing, and allows an external monitor to observe, control, and reconfigure the circuit during operation. Unlike currently available programmable logic devices this chip is targeted specifically at the development rather than the production environment. One or more of these chips could be wired into the development version of an application system, to add flexibility and simplify the design process by making the design more controllable and observable. In another type of application, an array of these chips could be assembled into a dedicated processor attached to a workstation. The architecture of the chip, some of the tradeoffs involved, and the CAD challenges needed to support it are outlined.<<ETX>>

The benefits of flexibility in lookup table-based FPGAs

FPGAs (field programmable gate arrays) need not be limited to a single fixed-size truth table in each block. The authors discuss the utility of allowing each blocks single large table (e.g. one 5-input, 32-b table) to be reconfigured into smaller tables (e.g. eight 4-b tables). Results describing the efficiency of packing some standard benchmark circuits into various configurations are presented and the cost/benefits discussed. It is shown that a logic block containing four lookup tables, each of which is 8-b RAM, is the best choice if only the area efficiency is considered. It is also shown that if circuit speed is considered, a logic block containing two lookup tables, each of which contains 16 b of RAM, is the best choice. >

ORCA: A New Architecture for High-Performance FPLs

AT&Ts ORCA (Optimized Reconfigurable Cell Array) architecture extends FPGA applicability into a larger domain than is possible with todays parts, including datapath intensive designs such as memory controllers, signal processing parts, and telecommunication interfaces. Key to the suitability of the ORCA for these jobs is the fact that each of its basic blocks is capable of processing four bits. So, for example, a 16 bit adder requires exactly 4 blocks, not 9 or 16 as in other architectures. Yet the total complexity of each block is comparable to other current parts, thus yielding a significant improvement in functional density.

An analysis of C machine support for other block-structured languages

Although the C machine proposed by Ditzel (et al.) was originally intended to execute the C programming language, its utility would be enhanced if it could also execute programs written in other languages. Of particular interest is the Ada programming language, in part because it is likely to be a standard for government work, but more importantly because its support requirements are typical of many modern languages such as CHILL, MESA, EUCLID, MODULA, and others. The most salient characteristics of the C machine, e.g. its stack cache and address modes, are seen to map well onto the Ada language. In fact, many of the arguments for these features are more compelling for the Ada language than they are for C. One exception is the way the stack cache may perform on a heavily multi-tasked program, but there is no obvious solution to this, even on much more complex machines like the VAX11-780.

Placement algorithms for CMOS cell synthesis

Heuristic placement algorithms for the layout synthesis of CMOS logic cells are described. The techniques are not restricted to fully complimentary CMOS, and focus on a novel strategy for FET pair ordering which takes advantage of splitting wide FETs to eliminate diffusion gaps. These algorithms are applicable to strip-based layout synthesis from transistor netlists. Existing CMOS cell synthesis systems neither fully include the costs nor utilize the benefits of FET splitting. The system described does this, in some cases results in an area saving. In general, it trades diffusion gaps for useful FETs. Since some technologies penalize diffusion gaps heavily, and others, such as sea-of-gates, forbid them altogether, such a tradeoff seems increasingly appropriate.<<ETX>>

Overview of the IDA System: A Toolset for VLSI Layout Synthesis

The Integrated Design Aides (IDA) toolset is a set of VLSI CAD software programs that have been developed to make the most effective use possible of a designer’s time. IDA incorporates a number a layout synthesis tools capable of generating both structured circuits, such as ALU’s, and random logic. The system centers around a constraint-based, symbolic language called IMAGES and a compacter methodology. This paper describes IDA, its capabilities, techniques, and status.