Nam-Tae Kim

Stability of operation versus temperature of a three-phase clock-driven chaotic circuit

We evaluate the influence of temperature on the behavior of a three-phase clock-driven metal—oxide—semiconductor (MOS) chaotic circuit. The chaotic circuit consists of two nonlinear functions, a level shifter, and three sample and hold blocks. It is necessary to analyze a CMOS-based chaotic circuit with respect to variation in temperature for stability because the circuit is sensitive to the behavior of the circuit design parameters. The temperature dependence of the proposed chaotic circuit is investigated via the simulation program with integrated circuit emphasis (SPICE) using 0.6-μm CMOS process technology with a 5-V power supply and a 20-kHz clock frequency. The simulation results demonstrate the effects of temperature on the chaotic dynamics of the proposed chaotic circuit. The time series, frequency spectra, bifurcation phenomena, and Lyapunov exponent results are provided.

A novel on-chip step-dimmer for low cost AC-powered HV-LED driver

This letter proposes a novel on-chip step-dimmer using an analog dimming method for a high PF AC-powered LED driver. The full AC LED driver can achieve a very high PF and a low THD by using a self-adaptive power processing circuit while delivering a best-in-class dimming performance with the proposed step-dimmer. Under the control of the dimming signal, the dimming voltage is step-adjusted from 1.0V to 2.5V, the average LED current can be changed from 40% to 100% of the nominal LED current value. To verify the feasibility of the proposed scheme, an 8-string 4.4WAC-powered LED driver with the proposed step-dimmer was designed and simulated using a 0.35 um-700V BCD Magnachip process. The gained results verify that the proposed step-dimmer can maintain a high performance of the AC LED driver under different dimming modes with a PF and a THD around 0.998 and 6%, respectively.

Design of a step-down DC-DC Converter for mobile LED applications

In this paper, a step-down converter for mobile LED applications is proposed. The converter which is operated with 4 MHz high switching frequency is capable of reducing mounting area of passive devices. It consists of a power stage and a control block. The power stage is composed of inductor, output capacitor, MOS transistors and feedback resistors, meanwhile, the control block consists of a pulse width modulator, an error amplifier and an oscillator etc. The proposed step-down converter has been designed and verified with a 0.35 /an 1-poly 4-metal BCD process technology. Simulation results show an output voltage of 1.8 V and output current of 100 mA for an input voltage of 3.7 V. The output current capability of the proposed converter is higher compared to the conventional 500 kHz driven converter (25~50 mA) with the duty ratio of 0.4.

Ultra-wideband bias-tee design using distributed network synthesis

This paper presents a design methodology for ultrawideband bias tees, using a distributed network synthesis considering both RF and DC performance. For the design of bias tees, transfer functions of distributed circuits are offered using equal ripple approximation, and DC current-handling capacity is incorporated into the network synthesis by calculating capacity in terms of the characteristic impedance of a transmission line. A bias-tee circuit with the desired characteristics can be synthesized by properly adjusting the minimum insertion loss (MIL) and ripple of the transfer function with reference to the required performance. As an example, a distributed network synthesis is applied to design a bias tee for ultra-wideband applications.

A voltage-controlled chaotic oscillator based on carbon nanotube field-effect transistor for low-power embedded systems

This paper presents a compact and low-power-based discrete-time chaotic oscillator based on a carbon nanotube field-effect transistor implemented using Wong and Dengs well-known model. The chaotic circuit is composed of a nonlinear circuit that creates an adjustable chaos map, two sample and hold cells for capture and delay functions, and a voltage shifter that works as a buffer and adjusts the output voltage for feedback. The operation of the chaotic circuit is verified with the SPICE software package, which uses a supply voltage of 0.9 V at a frequency of 20 kHz. The time series, frequency spectra, transitions in phase space, sensitivity with the initial condition diagrams, and bifurcation phenomena are presented. The main advantage of this circuit is that its chaotic signal can be generated while dissipating approximately 7.8 μW of power, making it suitable for embedded systems where many chaos-signal generators are required on a single chip.

Design of a PWM DC-DC Boost Converter IC for Mobile Phone Flash

In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

Fully integrated circuit design Aihara's chaotic neuron model

This paper presents design of the integrated chaotic neuron using 0.8 µm single poly CMOS technology, its dynamical behavior analysis. Proposed chaotic neuron consists of several op-amps, sample and hold circuits, a nonlinear function block for chaotic signal generation, a two-phase clock circuits and sigmoid output function block. From HSPICE simulation results of the circuit, approximated empirical equations is induced. Then the dynamical responses of the chaotic neuron such as bifurcation diagram, time series, Lyapunov exponent, and average firing rate are calculated with numerical analysis.

Circuit design of the complementary pixel structure for a wide dynamic range CIS

In this paper, we propose a new complementary image sensor pixel structure by improving the conventional 3TR pixel structure. Proposed complementary pixel structure for wide dynamic range CIS consists of photo diode, PMOS reset transistor, several PMOS and NMOS transistors for complementary signals. We show SPICE simulation results of the complementary image pixel structure for optimization. Proposed complementary pixel was fabricated with 0.5 µm 1-poly 2-metal standard CMOS process. From the measured results, output voltage of the proposed pixel is 0.8 V to 3.8 V in condition of the 5 V power supply. These output signals give enough chances to detect wide operation coverage.

OFD(Over Flow Drain) pixel architecture design of the CIS which has wide dynamic range with a CMOS process

We propose a new image pixel architecture which has OFD(Over Flow Device) node by improving conventional 3TR pixel structure. Newly designed pixel consists of photo diode which is verified with HSPICE simulation, PMOS reset transistor, several NMOS and several PMOS transistors. Photodiode signals from each PMOS and NMOS are detected by Reset PMOS. These output signals give enough chances to detect wide operation coverage because OFD node has overflow photocurrent. According to various light intensity, we analyzed characteristic of the output voltage with a SPICE tool. Proposed pixel output has specific value which can detect possible from to light intensity. It has wide-dynamic range of 160 dB.