Namita Sharma

Energy optimization in Android applications through wakelock placement

Energy efficiency is a critical factor in mobile systems, and a significant body of recent research efforts has focused on reducing the energy dissipation in mobile hardware and applications. The Android OS Power Manager provides programming interface routines called wakelocks for controlling the activation state of devices on a mobile system. An appropriate placement of wakelock acquire and release functions in the application can make a significant difference to the energy consumption. In this paper, we propose a data flow analysis based strategy for determining the placement of wakelock statements corresponding to the uses of devices in an application. Our experimental evaluation on a set of Android applications show significant (up to 32%) energy savings with the proposed optimization strategy.

Array Interleaving—An Energy-Efficient Data Layout Transformation

Optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. These techniques need to evolve with modern architectures supporting wide memory accesses. We investigate array interleaving, a data layout transformation technique that achieves energy efficiency by combining the storage of data elements from multiple arrays in contiguous locations, in an attempt to exploit spatial locality. The transformation reduces the number of memory accesses by loading the right set of data into vector registers, thereby minimizing redundant memory fetches. We perform a global analysis of array accesses, and account for possibly different array behavior in different loop nests that might ultimately lead to changes in data layout decisions for the same array across program regions. Our technique relies on detailed estimates of the savings due to interleaving, and also the cost of performing the actual data layout modifications. We also account for the vector register widths and the possibility of choosing the appropriate granularity for interleaving. Experiments on several benchmarks show a 6--34% reduction in memory energy due to the strategy.

Data memory optimization in LTE downlink

Optimizations related to memory accesses and data storage make a significant difference to the performance and energy of a wide range of data-intensive applications. Such strategies need to evolve with modern SoC and processor architectures, which lead to new optimization opportunities. In this paper, we focus on data memory optimization for LTE downlink receiver as this is a data- and computation-intensive part of the LTE application with tight energy and latency constraints. We study the data dependencies globally and conclude that by providing data samples from the antennas in interleaved form at the FFT input, we can achieve 7-15% reduction in memory access energy over an optimized implementation without any performance overhead.

Energy efficient data flow transformation for Givens Rotation based QR Decomposition

QR Decomposition (QRD) is a typical matrix decomposition algorithm that shares many common features with other algorithms such as LU and Cholesky decomposition. The principle can be realized in a large number of valid processing sequences that differ significantly in the number of memory accesses and computations, and hence, the overall implementation energy. With modern low power embedded processors evolving towards register files with wide memory interfaces and vector functional units (FUs), the data flow in matrix decomposition algorithms needs to be carefully devised to achieve energy efficient implementation. In this paper, we present an efficient data flow transformation strategy for the Givens Rotation based QRD that optimizes data memory accesses. We also explore different possible implementations for QRD of multiple matrices using the SIMD feature of the processor. With the proposed data flow transformation, a reduction of up to 36% is achieved in the overall energy over conventional QRD sequences.

Early exploration for platform architecture instantiation with multi-mode application partitioning

We present a systematic methodology for exploring application partitioning and assignment together with platform architecture instantiation. Streaming applications with multiple runtime modes are considered. The platform architecture is based on a domain specific MPSoC architecture template. We show results using complete inner modem physical layer processing of wireless applications, WLAN and LTE. We show that the proposed methodology obtains up to 30% energy improvement in energy with negligible area overheads as compared to straight-forward mapping to one processor, while meeting performance constraints, for a multi-mode WLAN 11n system and single-mode LTE system.

The packing radius of a poset block code

We investigate the properties of the packing radius of a code with respect to poset block metric. In the process, we have addressed a few minor errors in the paper, “The packing radius of a code and partitioning problems: The case for poset metrics”, in Proc. IEEE Int. Symp. Information Theory (2014), pp. 2954–2958 by D’Oliveira and Firer.

Array scalarization in high level synthesis

Parallelism across loop iterations present in behavioral specifications can typically be exposed and optimized using well known techniques such as Loop Unrolling. However, since behavioral arrays are usually mapped to memories (SRAM) during synthesis, performance bottlenecks arise due to memory port constraints. We study array scalarization, the transformation of an array into a group of scalar variables. We propose a technique for selectively scalarizing arrays for improving the performance of synthesized designs by taking into consideration the latency benefits as well as the area overhead caused by using discrete registers for storing array elements instead of denser SRAM. Our experiments on several benchmark examples indicate promising speedups of more than 10x for several designs due to scalarization.

Characterization of extended Hamming and Golay codes as perfect codes in poset block spaces

Alves, Panek and Firer (Error-block codes and poset metrics, Adv. Math. Commun., 2 (2008), 95-111) classified all poset block structures which turn the [8,4,4] extended binary Hamming code into a 1-perfect poset block code. However, the proof needs corrections that are supplied in this paper. We provide a counterexample to show that the extended binary Golay code is not 1-perfect for the proposed poset block structures. All poset block structures turning the extended binary and ternary Golay codes into 1-perfect codes are classified.

Perfect codes in poset spaces and poset block spaces

Abstract The paper begins by giving a counter example to show that the algorithm for construction of new perfect poset codes from a given perfect poset code by removal of a coordinate as given by Lee (2004) [11] does not hold. The algorithm has been improved and generalized to obtain new perfect poset block codes from a given perfect poset block code. The modified necessary and sufficient conditions for the construction of new perfect poset codes have been derived as a particular case. A bound has been obtained on the height of poset P s that turns a given π-code into r-perfect ( P s , π ) -code. We show that there does not exist a poset which admits the binary Simplex code of order 3 to be a 2-perfect poset code. Also, all the poset structures which admit the extended ternary Golay code to be a 3-perfect poset code have been classified.

Perfect codes in poset block spaces

There is a limited class of perfect codes with respect to the classical Hamming metric. There are other kind of metrics with respect to which perfect codes have been investigated viz. poset metric, block metric and poset block metric. Given the minimal elements of a poset, a necessary and sufficient condition for 1-perfectness of a poset block code has been derived. A necessary and sufficient condition for a poset block code to be r-perfect has also been considered. Further, for each r, 1 ≤ r ≤ n − k, a sufficient condition that ensures the existence of a poset block structure which turns a given code into an r-perfect poset block code has been obtained. Several illustrations of well known codes to be r-perfect for specific values of r have been explored.