Rishu Chaujar

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency fT, maximum oscillation frequency fmax, transconductance frequency product, higher order transconductance coefficients (gm1, gm3), VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HDGAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

TCAD RF performance investigation of Transparent Gate Recessed Channel MOSFET

In this paper, analog/RF performance and small signal behavior of Transparent Gate Recessed Channel (TGRC) MOSFET has been investigated in terms of transconductance, DIBL, channel resistance parasitic capacitances, cut-off frequency and maximum oscillator frequency. Results so obtained are compared with Conventional Recessed Channel (CRC) MOSFET at THz frequency range, using ATLAS-3D device simulator. Furthermore, the impact of technology parameter variations in terms of gate length (Lg) has also been evaluated. Result shows that there is 42% enhancement in cut-off frequency, 132% increment in maximum oscillator frequency and significant improvement in parasitic capacitances for TGRC-MOSFET due to reduced short channel effects (SCEs) and enhanced on-current driving capabilities thus, reflecting its significance in high-frequency THz range applications. TGRC-MOSFET improved analog and RF performance at THz frequency range.Enhancement in transconductance, reduction in parasitic capacitances and reduction in SCEs such as DIBL is observed.Improvement is perceived both in reflection and transmission coefficients as compared to CRC-MOSFET.42% Enhancement in cut-off frequency, 132% increment in maximum oscillator frequency is observed.TGRC-MOSFET is appropriate for high-performance System-On-Chip RF/microwave applications.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10−4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor

Abstract In the work proposed, linearity performance of dual material gate (DMG) AlGaN/GaN HEMT has been analyzed and compared with the corresponding performance of Single Material Gate (SMG) AlGaN/GaN HEMT using ATLAS device simulation. Specifically, we investigate the linearity of DMG and conventional AlGaN/GaN HEMT based on the linearity metrics such as gm, g m 2 , g m 3 , VIP2, VIP3, IIP3, IMD3 and 1-dB compression point. The impact of various device parameters on the device linearity such as the channel length, doping and thickness of the barrier and spacer layer, Al mole fraction and the work function difference of the two gate metals has also been investigated. It is observed that a suitably designed DMG AlGaN/GaN HEMT can considerably improve the linearity performance and minimize intermodulation distortion due to reduced drain induced barrier lowering and high-field effect; and a more uniform electric field for applications in 3-G mobile communication and low noise amplifiers.

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping (NA) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency (ft) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain (Gma), maximum transducer power gain (GMT), maximum unilateral power gain (MUG), maximum frequency of oscillation (fMAX) and stern stability factor (K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.

Novel SiC encapsulated coaxial silicon nanowire solar cell for optimal photovoltaic performance

In this paper, SiC encapsulated coaxial silicon (p-i-n) nanowire solar cell consisting of anti-reflective passivation layer (ARPL) has been designed and simulated. Photo reflectance is significantly reduced in the UV/visible spectral region due to the presence of SiC. The external quantum efficiency EQE>60% in the spectrum range of 325-625 nm wavelength and short circuit current density (Jsc), 26 mA.cm-2 as well as open circuit voltage (Voc), 291 mV has been observed. This results in 19% and 26% higher JSC and power conversion efficiency (PCE) compared to conventional SiO2 passivated coaxial nanowire silicon solar cell. Under one sun illumination (0.1 W/cm2), 4.3% PCE is achieved in SiC encapsulated coaxial silicon nanowire solar cell having the diameter and length of 300nm, 5.1μm respectively. Result indicates, SiC plays an important role in the photoelectric conversion. All the simulations have been done using calibrated software program in Silvaco atlas and devedit device simulator.

Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET

In this work, the temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET (HD-GAA-TFET) has been addressed, and the results are simultaneously compared with gate all around tunnel FET (GAA-TFET). This is done by investigating the effect of interface trap charges such as donor (positive interface charges) and acceptor (negative interface charges) on the device figure of merits. The performance has been compared in terms of switching parameters such as ION/IOFF ratio, Iqff, Iamb, subthreshold swing (SS) and threshold voltage (Vth). Results reveal that remarkable enhancement in ION/IOFF ratio and better reliability in case of HD GAA TFET outperforms its conventional counterparts, i.e., GAA TFET. All the simulations have been done on ATLAS device simulator.

Rear contact solar cell with ZrO2 nano structured front surface for efficient light trapping and enhanced surface passivation

In the present work, the impact of ZrO2 textured front surface on rear contact solar cell has been studied. The efficient light trapping and lower surface recombination rate about ~ 1020 /cm3s has been observed. Result shows, significant improvement in device photovoltaic parameters compared to conventional cell. The 29% higher short circuit current density (Jsc) and 31% higher power conversion efficiency (PCE) compared to planar rear contact cell has been obtained. The Jsc, 28.6 mA/cm2 and open circuit voltage (Voc), 623mV has been obtained. This results in 14.3% PCE in sub-10μm-thick device. Finite difference time domain (FDTD) method results in 15.1% PCE. All the simulation have been done using calibrated software program in atlas device simulation.

Effect of dielectric engineering on analog and linearity performance of gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET

This work demonstrates that with the incorporation of gate stack (GS) on GEWE-SiNW MOSFET, the analog and linearity performance of the device enhances in terms of transconductance, output conductance and device efficiency. The important Linearity figure of merits (FOMs) such as second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order input intercept point (IIP3), third order intermodulation distortion (IMD3) and 1-dB compression point are studied with the help of 3D ATLAS and DEVEDIT device simulator for low power linear CMOS devices. Moreover, it has been observed that the zero-cross over point for GS-GEWE-SiNW MOSFET is reduced appreciably compared to its counterparts, which results into lowered optimum bias point for device operation.

Novel 4-terminal perovskite/SiC-based rear contact silicon tandem solar cell with 27.6 % PCE

In this work, a novel 4-terminal perovskite / SiC-based rear contact silicon tandem device has been proposed for long-term cost reduction and higher efficiency. The novel tandem device proposed in this work shows ultra-high power conversion efficiency (PCE) of 27.6 % and 22.7 % with 300 μm and 10 μm thick rear contact Si solar cell, respectively. The realistic TCAD simulation has been performed for Methylammonium lead triiodide perovskite cell. To simulate and predict the realistic behavior of the device, all the fundamental recombination mechanisms have been included in CH3NH3PbI3 film during the simulation. The perovskite device which is used as top cell shows PCE of 19.9% which is almost equivalent to experimentally available record efficiency of 20.1%. The charge carrier decay constants for CH3NH3PM3 used in the simulation have been obtained from experimentally available data.