Nan Qi

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration

A fully integrated dual-channel reconfigurable GNSS receiver supporting Compass/GPS/GLONASS/Galileo systems is implemented in 65 nm CMOS. The receiver incorporates two independent channels to receive dual-frequency signals simultaneously. GNSS signals located at the 1.2 GHz or 1.6 GHz bands are supported, with their bandwidths programmable among 2.2 MHz, 4.2 MHz, 8 MHz, 10 MHz, and 18 MHz. By implementing a flexible frequency plan with a low/zero-IF architecture and reconfigurable analog baseband circuits, only one frequency synthesizer is required to provide the local oscillator (LO) frequency for two channels, thereby avoiding any LO crosstalk. Analog baseband circuits employ operational amplifiers that are capable of power scaling, in order to minimize power consumption across different operating modes. An I/Q mismatch calibration module placed prior to the complex-IF bandpass filter is implemented to improve the image rejection ratio. The receiver achieves a minimum 1.88 dB noise figure, an average 50 dB image rejection ratio, and a 64 dB dynamic range with 1 dB steps of gain-adjustment, with a total power consumption of 31-44 mW. Finally, experimental verification combining both the receiver and a digital baseband shows a positioning result comparable to commercial chips.

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS

Silicon photonics devices offer promising solution to meet the growing bandwidth demands of next-generation interconnects. This paper presents a 5 × 25 Gb/s carrier-depletion microring-based wavelength-division multiplexing (WDM) transmitter in 65 nm CMOS. An AC-coupled differential driver is proposed to realize 4 × VDD output swing as well as tunable DC-biasing. The proposed transmitter incorporates 2-tap asymmetric pre-emphasis to effectively cancel the optical nonlinearity of the ring modulator. An average-power-based dynamic wavelength stabilization loop is also demonstrated to compensate for thermal induced resonant wavelength drift. At 25 Gb/s operation, each transmitter channel consumes 113.5 mW and maintains 7 dB extinction ratio with a 4.4 V pp-diff output swing in the presence of thermal fluctuations.

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS

A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable low-power (1.3 mW) and low-voltage (0.6 V) operation. Implemented in 65 nm CMOS, this work is compatible with the IEEE 802.15.6 (WBAN) narrowband physical layer specification and achieves -91 dBm and -96 dBm sensitivity at 10-3 BER for π/4-DQPSK and π/2-DBPSK modulation respectively. The proposed highly digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~ 0.35 mm2 in 65 nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on WBAN demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.

Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver

A power-scalable reconfigurable filter with in-phase/quadrature (I/Q) imbalance calibration for a multimode Global Navigation Satellite Systems (GNSS) receiver is presented. The filter is reconfigurable as either a fifth-order complex bandpass filter exhibiting a tunable intermediate frequency (4.092, 6.138, 10.23, 12.296, 13.29, 18.4, and 20.442 MHz) and bandwidth (2.2, 4.2, 8, 10, and 18 MHz) or a third-order low-pass filter with tunable bandwidth (5 and 9 MHz). A flexible current-reuse operational amplifier with a power-scaling technique is proposed to lower the power consumption, and the image-rejection ratio is improved by almost 20 dB by introducing an I/Q imbalance calibration circuit before the filter. The filter, which was implemented in 65-nm CMOS, consumes 2.9-19.5 mW in different modes, with the I/Q calibration circuit consuming 0.9 mW.

A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS

A fully-integrated dual-channel reconfigurable GNSS receiver supporting GPS/Compass/Galileo/GLONASS in 65nm CMOS is presented. The receiver has two independent channels to support simultaneous dual-frequency reception, and can be reconfigured to receive various GNSS signals located in 1.2GHz or 1.57GHz band, which have different signal bandwidth including 2.2MHz, 4.2MHz, 8MHz, 10MHz and 18MHz. By flexible frequency plan, low-IF/zero-IF architecture switching and flexible analog baseband circuits, only one frequency synthesizer is adopted to provide local oscillation (LO) for two channels simultaneously, which could avoid the LO crosstalk issue. Analog baseband circuits employ operational amplifiers capable of power scaling to optimize power consumption among various mode operations. Besides, an I/Q mismatch calibration module placed ahead of the IF complex bandpass filter is implemented to improve image rejection ratio. The receiver finally achieves 2.2dB noise figure, an average of 50dB image rejection ratio, and 64dB dynamic range with 1dB gain-adjusting steps, while consuming a minimum of 31mW power.

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS

Silicon photonic microring modulators (MRMs) offer a promising approach for realizing energy-efficient wavelength-division multiplexing (WDM) optical interconnects. For data-rates greater than 10Gb/s, depletion-mode MRMs are generally preferred over their injection-mode counterparts due to their shorter carrier lifetimes and resulting higher bandwidths. Unfortunately, these depletion-mode MRMs typically exhibit low PN junction tunability, thereby requiring higher modulation voltages in order to provide >6dB extinction ratios (ER). Furthermore, negative DC-biasing of the MRMs is necessary to maintain reverse-biased depletion-mode operation. In this work, a 5×25Gb/s hybrid-integrated MRM WDM transmitter is demonstrated that incorporates the following key advances: 1) an AC-coupled differential output driver that applies a 4.4Vpp-diff output-swing on the MRM while providing a tunable on-chip negative DC-bias; 2) a 2-tap non-linear digital FFE that compensates for optical-dynamics-induced bandwidth limitations; 3) a dynamic thermal tuning loop that stabilizes the MRM by minimizing thermally-induced wavelength fluctuations.

A 2.7-mW 1.36–1.86-GHz LC-VCO With a FOM of 202 dBc/Hz Enabled by a 26%-Size-Reduced Nano-Particle-Magnetic-Enhanced Inductor

This paper reports the first LC voltage-controlled oscillator (LC-VCO) in CMOS utilizing a novel nontraditional compact inductor with integrated vertical nano particles magnetic core (Ni-Zn-Cu) to improve the figure-of-merit (FOM) of the VCO circuit. The new magnetic-enhanced inductor, fabricated in an integrated-circuit back-end using a CMOS-compatible process, improves inductance density ( L-density) and quality factor ( Q-factor) up to 7 GHz. A 1.36-1.86-GHz VCO with a nano-ferrite-integrated inductor was fabricated in a 180-nm RF CMOS. Measurements show that the magnetic-cored inductor improves the L-density and Q-factor by 49.8% and 59.2% at 1.8 GHz, respectively, while reducing the size by 26%. The VCO achieves reduced power consumption of 2.7 mW at a 1.8-V supply, low phase noise of less than -121, and -126 dBc/Hz at 100-kHz and 1-MHz frequencies offset, and a high FOM of 202 dBc/Hz. This prototype VCO demonstrates that the new vertical-nano-magnetic-cored inductor technology is a potential solution to high-performance low-cost compact RF systems-on-chip.

A hybrid approach to I/Q imbalance self-calibration in reconfigurable low-IF receivers

This paper presents a power detection based I/Q imbalance self-calibration technique to compensate signal path gain and phase mismatch in a reconfigurable low-IF receiver. The calibration can be carried out at startup to improve the image rejection ratio (IRR) of the IF complex-bandpass filter, and then configuration words are saved. The system employs an analog I/Q calibration module to adjust signal path gain and phase mismatch, a power detector to measure I/Q imbalances, digital circuits to implement the calibration algorithm, and a digital AGC to adjust IF signals within a predetermined level. The self-calibration system is implemented as a part of a multi-mode GNSS (Global Navigation Satellite Systems) receiver. Only one 2-bit ADC in I (or Q) path is needed to sample the analog IF signal. Measurement results show that the calibrated IRR achieves an average of 50dB in different operation modes which gets a 10~20dB improvement. The low-IF GNSS receiver is fabricated in 65nm CMOS process, and the digital part of the self-calibration system is implemented in a FPGA.

A 25Gb/s, 520mW, 6.4Vpp Silicon-Photonic Mach-Zehnder Modulator with distributed driver in CMOS

A 25Gb/s heterogeneously-integrated Silicon-Photonic transmitter is designed entirely in CMOS, consisting of a high-swing driver wire-bonded to a MZ modulator. Measurement results demonstrate clean optical eye diagrams with > 4dB extinction ratio while consuming 0.52W.

9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS

The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBAN). The power dissipation, supply voltage, and IC area are some of the most important criteria for successful WBAN implementations. Analog-intensive heterodyne receivers (RX) have been previously demonstrated, consuming 4 to 5mW of power from a 1-to-1.2V supply while occupying large silicon area, due to the presence of area-intensive analog building blocks such as low-pass filters at the IF [1,2]. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in power consumption and area, but require system and circuit-level innovations to achieve desired sensitivity and linearity. This paper presents a mostly-digital 2.4GHz RX architecture that uses a sub-sampling technique with digital IF/baseband signal processing to enable low-power (1.3mW) and low-voltage (0.6V) operation, resulting in ~3x reduction in power consumption. Early analog-to-digital conversion leads to the IC occupying only 0.35mm2 of active silicon area. While the IC focuses on WBAN demodulation, the presented techniques are applicable to other low-power standards as well.