Rui Bai

Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

Photonic interconnects are a promising technology to meet the bandwidth demands of next-generation high-performance computing systems. This paper presents silicon photonic transceiver circuits for a microring resonator-based optical interconnect architecture in a 1 V standard 65 nm CMOS technology. The transmitter circuits incorporate high-swing ( 2Vpp and 4Vpp) drivers with nonlinear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 Gb/s operation, the 4Vpp transmitter achieves 12.7 dB extinction ratio with 4.04 mW power consumption, excluding laser power, when driving wire-bonded modulators designed in a 130 nm SOI process, while a 0.28 nm tuning range is obtained at 6.8 μW/GHz efficiency with the bias-based tuning scheme implemented with the 2Vpp transmitter. When tested with a wire-bonded 150 fF p-i-n photodetector, the receiver achieves -9 dBm sensitivity at a BER=10-9 and consumes 2.2 mW at 8 Gb/s. Testing with an on-die test structure emulating a low-capacitance waveguide photodetector yields 17 μApp sensitivity at 10 Gb/s and more than 40% power reduction with higher input current levels.

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver

Silicon photonic links based on ring-resonator devices provide a unique opportunity to deliver distance-independent connectivity, whose pin-bandwidth scales with the degree of wavelength-division multiplexing. However, reliability and robustness are major challenges to widespread adoption of ring-based silicon photonics. In this work, a CMOS photonic transceiver architecture is demonstrated that incorporates the following enhancements: transmitters with independent dual-edge pre-emphasis to compensate for modulator bandwidth limitations; a bias-based tuning loop to calibrate for resonance wavelength variations; and an adaptive sensitivity-bandwidth receiver that can self-adapt for insitu variations in input capacitance, modulator/photodetector performance, and link budget.

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization

Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1-3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity.

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a per-data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER <; 10-12 across a 20-cm FR4 PCB channel.

DWDM silicon photonic transceivers for optical interconnect

We present energy-efficient microring resonator-based silicon photonic transceivers for DWDM optical interconnect.

2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS

In this work, a DFE is presented that is designed specifically to operate at low VDD and scale well in energy-efficiency. To achieve this goal, the following innovations are introduced: 1) fast and energy-efficient charge-based latch and sample-and-hold (S/H) topologies; 2) a CMOS-clocked quarter-rate DFE architecture with summer gain and power optimization; 3) an integrating summer with a compact common-mode restoration circuit. Leveraging these techniques, the DFE is capable of operating at or below 0.7V, with an energy efficiency of or better than 0.25pJ/bit.

A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization

Single-mode wavelength-division multiplexing (WDM) optical links are an attractive technology to meet the growing interconnect bandwidth demand in data center applications. This paper presents a multi-channel hybridintegrated photonic receiver based on microring drop filters and waveguide photodetectors implemented in a 130 nm SOI process and high-speed optical front-ends designed in 65 nm CMOS. The source-synchronous receiver utilizes an LC injection-locked oscillator (ILO) in the clock path for improved jitter filtering, while maintaining correlated jitter tracking with the data channels. Receiver sensitivity is improved with a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE). In order to stabilize the microring drop filter resonance wavelength, a peak-detector-based thermal tuning loop is implemented with a 0.7 nm range at 43 μW/GHz efficiency. When tested with a waveguide photodetector with 0.45 A/W responsivity, the receiver achieves -8.0 dBm OMA sensitivity at a BER = 10-12 with a jitter tolerance corner frequency near 20 MHz and a per-channel power consumption of 17 mW including amortized clocking power.

Hybrid integrated DWDM silicon photonic transceiver with self-adaptive CMOS circuits

We present a DWDM silicon photonic transceiver with self-adaptive CMOS circuits. The energy efficiency is 808fJ/bit at 5Gbps for a ring-modulator based transmitter and 275fJ/bit at 8Gbps with BER<;10-15 for the receiver.

Silicon Photonic Microring Resonator-Based Transceivers for Compact WDM Optical Interconnects

This paper examines the potential of silicon photonic microring resonator-based optical transceivers for compact wavelength-division multiplexing (WDM) optical interconnects. An overview of the photonic devices typically found in a ring resonator optical interconnect platform is provided and the design of transceiver circuits which address key challenges related to the modulators and drop filters is described. The possibility of further improvements in bandwidth density via efficient implementations of >50Gb/s PAM4 modulation with the microring modulators is detailed.

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS

A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<;10-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at VDD=0.8V.