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Dive into the research topics where Naoki Yasui is active.

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Featured researches published by Naoki Yasui.


Japanese Journal of Applied Physics | 2004

Energy control of incident ions to the chamber-wall by using Push-Pull bias (phase-controlled bias) in UHF-ECR etching system

Masahiro Sumiya; Naoki Yasui; Seiichi Watanabe

The effect of Push–Pull bias (phase-controlled bias) on the plasma potential and sputtering at the chamber-wall was investigated. It was found that the plasma potential could be controlled unrelated to the geometrical configuration of the chamber by using phase-controlled bias. The reason is that by using phase-controlled bias in the plasma with a magnetic field, the earth function of both electrodes facing each other can be controlled. Specifically, with the phase difference set to 180 degrees, the plasma potential was minimized and the decreased energy of incident ions to the chamber-wall reduced sputtering at the chamber-wall. Therefore, a stable process performance without particles caused by a sputtering at the chamber-wall, was expected by using Push-Pull bias in the dielectric UHF-ECR etching system.


Proceedings of SPIE | 2010

Application of model-based library approach to photoresist pattern shape measurement in advanced lithography

Naoki Yasui; Miki Isawa; Toru Ishimoto; Kohei Sekiguchi; Maki Tanaka; Mayuka Osaki; Chie Shishido; Norio Hasegawa; Shaunee Cheng

The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching. Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50% CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step, agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.


Proceedings of SPIE | 2010

Study on practical application to pattern top resist loss measurement by CD-SEM for high NA immersion lithography

Toru Ishimoto; Naoki Yasui; Norio Hasegawa; Maki Tanaka; Shaunee Cheng

With semiconductor technology moving to smaller patterns after the 45nm hp node, introduction of high-NA immersion lithography progresses, and with it, the challenge of decreasing process latitude. The decreasing lithography tool focus margin is mentioned as one of the key problems of a high-NA immersion lithography process. Tool focus fluctuation has an impact on resist pattern shape and not only does CD change, pattern height also decreases. As a result of previous studies [1][2], it is understood that the resist loss influences pattern formation after etch, and it was confirmed that resist loss is important for CD control. We observe correlation between the resist top roughness and the resist loss, and evaluate the resist loss measurement function by quantifying the resist top roughness. This principle of resist loss detection by measuring roughness is that a changing roughness of resist pattern top is detected as a fluctuation in image brightness on the CD-SEM. A measurement idea was proposed and performance evaluation has already been performed by using one kind of sample. In this study, we demonstrate the validity of resist loss detection by investigating various wafer conditions which contain the dependency by looking at two types of resist and different exposure tool illumination settings. Furthermore, we have confirmed the sensitivity limit of resist loss detection which is approximately above 10nm. Finally, we have discussed improving the resist loss detection sensitivity and considered the applicability of resist loss detection for the litho process monitor.


Archive | 2005

Plasma processing apparatus and method with controlled biasing functions

Masahiro Sumiya; Naoki Yasui; Seiichi Watanabe


Archive | 2001

Plasma processing apparatus and method using active matching

Masahiro Sumiya; Naoki Yasui; Seiichi Watanabe; Hitoshi Tamura


Archive | 2004

Plasma processing apparatus having high frequency power source with sag compensation function and plasma processing method

Naoki Yasui; Seiichi Watanabe; Masahiro Sumiya; Hitoshi Tamura


Archive | 2004

Plasma processing apparatus using active matching

Masahiro Sumiya; Naoki Yasui; Seiichi Watanabe; Hitoshi Tamura


Archive | 2010

Sample processing device, sample processing system, and method for processing sample

Seiichi Watanabe; Yutaka Kozuma; Tooru Aramaki; Naoki Yasui; Norihiko Ikeda; Hiroaki Takikawa


Archive | 2010

Sample treatment device, sample treatment system, and method for treating a sample

Seiichi Watanabe; 渡辺 成一; Yutaka Kouzuma; 豊 高妻; Tooru Aramaki; 荒巻 徹; Naoki Yasui; 安井 尚輝; Norihiko Ikeda; 紀彦 池田; Hiroaki Takikawa; 博昭 瀧川


Archive | 2010

Sample processing apparatus, sample processing system, and method for processing sample

Seiichi Watanabe; Yutaka Kozuma; Tooru Aramaki; Naoki Yasui; Norihiko Ikeda; Hiroaki Takikawa

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