Toru Ishimoto

Resist roughness evaluation and frequency analysis: metrological challenges and potential solutions for extreme ultraviolet lithography

Roughness of lithographic patterns is typically expressed as the absolute 3σ variation of resist lines by means of edge variation. How- ever, full characterization of the roughness requires both its amplitude and frequency distribution. This necessity arises from the requirement to re- duce different roughness frequencies for different lithographic levels. The International Technology Roadmap of Semiconductors (ITRS) has estab- lished a dedicated specification for low frequency roughness. To obtain full knowledge of the roughness behavior in the frequency domain, a power spectral density analysis technique is used. It is found that power spectral density has a unique profile for each process. Moreover, the major con- tribution to the roughness came from the low frequencies range. Besides this, an on-line metrological study on scanning electron microscopy re- sist roughness repeatability is executed to optimize the capturing image parameters and estimate eventual short- (daily) and long-term (yearly) contributions. In the end, 0.2-nm 3σ line width roughness stability value is found. To verify the validity of analysis and metrology, 32-nm extreme ultraviolet lithography exposures at different flare levels, 45-nm ArF im- mersion lithography through dose, and a rinse postlithography smoothing process are characterized with the aim to highlight the importance of low frequency roughness detection. C 2010 Society of Photo-Optical Instrumentation

Enabling CD SEM metrology for 5nm technology node and beyond

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

Application of model-based library approach to photoresist pattern shape measurement in advanced lithography

The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching. Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50% CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step, agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.

Advanced process control for hyper-NA lithography based on CD-SEM measurement

With the recent introduction of immersion lithography, optical systems with numerical aperture (NA) reaching 1.0 or larger can be realized. Various Resolution Enhancement Techniques (RET) such as various phase shift mask approaches have been used to push even further the resolution limit by reducing k1 scaling factor, including Double Patterning Technology. However, with the improved resolution by Hyper-NA and Low-k1, lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. Throughout the industry, Process Window has been widely used as an analytical tool to evaluate process latitude for a given design feature size; therefore, the ability to accurately and efficiently derive a Process Window within which a process can run on target and in control is fundamental to Low-k1 lithography. Accuracy of Process Window derivation is based on the ability to accurately measure and model the physical dimension of the design feature and how it changes in response to changes in process parameters. In the case of lithography, the Process Window of a desired critical dimension target is bounded by changes in exposure energy and defocus. To be able to accurately measure the physical dimension of the design feature remains a big challenge for metrologists especially in the presence of other process noise. In this work, it is shown that the precision of PW measurement can be enhanced by using CD-ACD (Average CD) function to measure a FEM (Focus-Exposure matrix) wafer. ACD is a function, which simultaneously measures several points, thus providing higher precision measurement in comparison to the conventional single point measurement. As seen in this work, by using ACD measurements to derive the Process Window, there is a significantly improvement in the stability of the derived Process Window. Also reported is the MPPC (Multiple Parameters Profile Characterization) *1), a function which provides the ability to extract pattern shape information from a measured e-beam signal. This function together with the ACD function enables PW measurement with high precision, which also takes into account the actual pattern shape. PW derived from conventionally measured data was compared with PW derived from ACD and MPPC measurement and we were able to demonstrate an improvement of more than 30% in precision of PW determination.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Abstract. The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

Contour-based metrology for complex 2D shaped patterns printed by multiple-patterning process

We developed a new measurement method enabling to quantitatively and accurately evaluate 2D pattern shapes, which becomes critical in patterning control of Metal layer patterns transferred by Litho-Etch-Litho-Etch (LELE) process. In LELE, a split patterning of a Metal-A (MA) layer and a Metal-B (MB) layer makes patterning control more challenging. Hence, it is essential to evaluate the shape of transferred patterns after final etching in order to verify that the patterning control of MA and MB layer patterns is performed within an allowable budget. For this, our Pattern Shape Quantification (PSQ) method [1][2][3], which enables to measure dimensional difference of the transferred pattern shape from their target-design, is an effective metrology. Patterns transferred through a LELE process contain the effects of two types of shape modifications. The first is the fidelity of the individual pattern shapes (e.g. pattern-end pull-back or push-out) whose determinative factors are adopted design (e.g. OPC and SRAF), process condition (of e.g. lithography and etching), etc. The second is the shift in position between MA and MB patterns induced by Pattern Placement Error (PPE) of MB with respect to MA. That means that the edge-placement errors (EPE) in the final pattern are not only due to the fidelity of the transferred pattern shape, but are also impacted by the PPE. Also, a space between MA and MB patterns will be affected by the PPE as well. A failure to maintain a required minimum space between patterns could lead to a leak-current between patterns (and hence directly affect device performance), so it is important that the PPE can be measured accurately. Therefore, we developed a method to measure local PPE in actual device patterns, from CD-SEM images, that also outputs a pattern-contour in which this PPE has been removed. Utilizing such a pattern-contour into the PSQ method enables to quantitatively determine the fidelity of transferred pattern shape solely induced by the 1st shape modification, while providing PPE data from the device patterns themselves. We believe that a high-quality patterning control (by e.g. optimization of process condition) of MA and MB can be performed only by using such a measurement result. This paper demonstrates and discusses the capability and effectiveness of our newly developed method.

Advanced CD-SEM metrology to improve total process control performance for hyper-NA lithography

In this research, we improved litho process monitor performance with CD-SEM for hyper-NA lithography. First, by comparing litho and etch process windows, it was confirmed that litho process monitor performance is insufficient just by CD measurement because of litho-etch CD bias variation. Then we investigated the impact of the changing resist profile on litho-etch CD bias variation by cross-sectional observation. As a result, it was determined that resist loss and footing variation cause litho-etch CD bias variation. Then, we proposed a measurement method to detect the resist loss variation from top-down SEM image. Proposed resist loss measurement method had good linearity to detect resist loss variation. At the end, threshold of resist loss index for litho process monitor was determined as to detect litho-etch CD bias variation. Then we confirmed that with the proposed resist loss measurement method, the litho process monitor performance was improved by detection of litho-etch CD bias variation in the same throughput as CD measurement.

The need for LWR metrology standardization: the imec roughness protocol

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Advanced full-automatic inspection of copper interconnects

The early detection of Cu sub-surface voids in nano-interconnects has become a main challenge with the reduction of the critical dimensions of the interconnects. A new methodology for full wafer Cu void inspection with high sensitivity and high speed has been developed using a Multi-Purpose SEM (MP-SEM) using high accelerating voltage, high resolution and multi BSE detectors. This inspection methodology has been used to evaluate the Cu metallization quality in nanointerconnects. The effectiveness of this inspection methodology was proven through the evidence of relations between Cu void density, trench widths, pattern density, and surrounding dummy structures.

Evaluation of roughness transfer from Litho to Etch using CD-SEM

Roughness transfer from Litho to Etch has been evaluated. The impact of Line width roughness (LWR) or Line edge roughness (LER) is getting larger with shrink of semiconductor devices. In this study, the roughness measurement by using a single frame SEM image was brought in to avoid resist shrinkage, and image enhance technique is used to compensate low S/N ratio in this one frame image. CD-AFM was used as reference, and LWR measured by CD-AFM was compared to the results of one frame enhanced image taken by CD-SEM. And roughness spectrum analysis was used for evaluation of roughness characteristics taken by CD-SEM and CD-AFM, and its transition by resist shrink or by etching process. It was enabled to observe the resist roughness profile with minimum shrink by using one frame enhanced image, then roughness transfer between Litho and Etch was evaluated by comparing in exactly the same position as pre- and post-etch. As a result, it was confirmed that transferred roughness by etching was remaining the peak and valley profile in resist observed by CD-SEM, but the roughness amplitude was reduced in higher frequency domain. This result consists with the roughness characteristics comparison from Litho to Etch. This also means roughness characteristics analysis shows the actual nanoscopic event.