Naoshi Yanagisawa

A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit

This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. Recently, the widest span of the input frequency has reached 640 times. Although the large divider ratio of the feedback divider relaxes the variation by lowering the VCO gain, the variation of the charge pump current reaches 6400 times in using conventional methods. The new method moderates the variation by changing the gain of the VCO and the capacitance of the loop filter in addition to the charge pump current. Loop filters in the PLL have been evolving along with the improvement of adaptive-biased PLLs. Switched capacitor type loop filters (SC-LPFs) are tolerable to wide variation of the cutoff frequency and preferable for reducing the pattern jitter which appears remarkably on the PLL with high divider ratio. However, the conventional SC-LPF is slightly complex. Thus, the simple 3-phase SC-LPF which realizes the fully flat response has been developed