Shiro Sakiyama

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback

An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging feedback (VAF) concept is proposed to overcome conventional relaxation oscillator problems such as sensitivity to comparator delay, aging, and flicker noise of current sources. A test-chip with typical frequency of 14.0 MHz was fabricated in a 0.18 μm standard CMOS process and measured frequency variations of ±0.16 % for supply changes from 1.7 to 1.9 V and ±0.19% for temperature changes from -40 to 125°C. The prototype draws 25 μA from a 1.8 V supply, occupies 0.04 mm2, and achieves 7x reduction in accumulated jitter (at 1500th cycle) as compared to a oscillator without VAF.

An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique

An on-chip DC/DC converter with high efficiency and low-noise and easy implementation in LSIs is needed for single-supply voltage and low-power operation of LSIs. To obtain high-efficiency, fixed pulse-width modulation (PWM) and zero volt switching (ZVS) adaptive control are used. Operation with efficiency >90% is reported. However, these reports do not discuss low- noise switching operation and easy implementation. These are the most important points for practical use. The specifications for the DC/DC converter are: (1) easy implementation into LSIs as an on-chip DC/DC converter; (2) efficiency over 90% (at Io=80 mA, 3.0 V->2.0 V); (3) output noise below 30 mVp-p. A DC/DC converter which has both efficiency over 92% and 15 mV output noise is incorporated into an LSI.

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage

Recently, on-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as DDR I/F and HDMI (for initial negotiation), and SoCs. RC oscillators (including relaxation oscillators) were developed to realize on-chip oscillators with standard CMOS processes. In this paper, a power-averaging feedback (PAF) concept for accurate oscillators with low power and small area is presented.

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge, which is one of the reasons for the 105mW power consumption at 12.5MS/s. In [2], 8× oversampling and a static current pre-amplifier for the comparator improve SNR to 88dB, but the ADC still consumes 66mW. In [3], digital calibration achieves an SNDR of 71dB at 3mW, but double conversion limits the sampling speed to 22.5MS/s.This paper describes a SAR ADC with 71dB SNDR that runs at 50MS/s and consumes 4.2mW. The ADC uses 3 SNDR-enhancement techniques that utilize noise and that have good compatibility to low-voltage fine digital processes.

A 69.8 dB SNDR 3 rd -order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver

This paper presents a 3rd-order continuous time delta-sigma modulator for a worldwide digital TV-receiver whose SNDR is 69.8 dB. An ultimate low power tuning system using RC-relaxation oscillator is developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing very compact circuit. The mechanism to occur 2nd-order harmonic distortion at current feedback DAC was analyzed and a reduction scheme of the distortion enabled the modulator to achieved FOM of 0.18 pJ/conv-step.

Mixed body-bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization

In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the analog design, including low power and small area, designers have to select an optimal solution among large combination of the following alternatives: which architecture should be adopted; what type of transistors should be taken; and whether digitally assisting technologies should be used or not, etc. A design based on experience and intuition cannot lead to the optimum in a short time. A comprehensive approach to the optimization, based on circuit theory, is now required. Convex optimization procedure can solve the formulae which represent circuit performance with over hundreds of design variables. We have constructed optimization environments for pipelined and delta-sigma analog-to-digital converters (ADCs) in consideration of the digitally assisting techniques and layout constraints. Both 12-bit pipelined ADCs and a 5th-order delta-sigma modulator were designed with the optimizer, and achieved top-ranked power efficiency.

Mixed body-bias techniques with fixed Vt and Ids generation circuits

In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, 85% reduction of the delay variation, and 75% improvement of power consumption of SRAM on a mobile processor.

A 200 MIPS image signal multiprocessor on a single chip

An image signal multiprocessor (ISMP) that is composed of four processor elements (PEs) and a main controller and is designed for general-purpose local image processing or feature extraction is described. The processor uses parallel processing and a CMOS process providing integration density 10 times larger than that of a bipolar process. As a result, it operates at 200 MIPS with a 12-b precision. The ISMP has 300 K transistors on a 14.4*13.7-mm chip fabricated with 1.2- mu m double-metal CMOS process technology and is mounted in 176-pin grid array. The power dissipation is 2.9 W from a single 5-V power supply. Four PEs are the most suitable tradeoff between speed and integration level. The main controller controls start of execution, data input, data output, and PE program loading. The ISMP has five image input ports accepting five vertical image data.<<ETX>>

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large increase of power, several SNR and SFDR enhancement techniques are proposed. Firstly, the ADC repeats comparison of LSB by using redundant DAC to average comparator noise and improve SNR. The technique also corrects settling error adaptively, which extends operation speed to 50 MHz even though extra comparison period is added for averaging. Secondly, simple filtering method for reducing DAC noise is introduced to achieve further improvement of SNR. Finally, new dithering method is proposed to enhance SFDR. Injecting noise-shaped, multi-valued and uniform-distributed dither to input of the ADC, spurs caused by capacitance mismatches of DAC can be suppressed more effectively compared with conventional dithering. These techniques can be realized by simple circuits in addition to a basic SAR ADC configuration and do not need high power consumption. The chip is fabricated in a 90 nm CMOS process and occupies 0.1 mm 2 including all correction logic. The ADC achieved a peak figure of merit (FoM) of 168.7 dB.