Naoto Miyamoto

Large-Scale Test Circuits for High-Speed and Highly Accurate Evaluation of Variability and Noise in Metal--Oxide--Semiconductor Field-Effect Transistor Electrical Characteristics

To develop a new process technology for suppressing the variability and noise in metal–oxide–semiconductor field-effect transistors (MOSFETs) for large-scale integrated circuits, accurate and rapid measurement test circuits for the evaluation of a large number of MOSFET electrical characteristics were developed. These test circuits contain current-to-voltage conversion circuits and simple scanning circuits in order to achieve rapid and accurate evaluation for a wide range of measurement currents. The test circuits were fabricated and the variabilities and noises in drain–source current, gate leakage current, and p–n junction leakage current were evaluated using a large-scale test circuit.

A small-area high-performance 512-point 2-dimensional FFT single-chip processor

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource saving multi-datapath radix-2/sup 2/ computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 /spl times/ 2.8 mm/sup 2/ with CMOS 0.35 /spl mu/m triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 /spl mu/sec and a 2-dimensional one in only 23.8 msec at 133 MHz operation.

Development of a CAD tool for 3D-FPGAs

This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A∗) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.

Analysis of Hundreds of Time Constant Ratios and Amplitudes of Random Telegraph Signal with Very Large Scale Array Test Pattern

Random telegraph signal (RTS) noise shows discrete and stochastic switching in two or more states at a drain current or threshold voltage. The capture and emission of carriers in individual traps near a silicon–gate insulator film interface induce RTS noise phenomena. RTS noise has become a crucial problem in analog devices and other devices. To suppress RTS noise, it is necessary to determine the energy level of traps. Time constant ratio has a strong relationship with the energy level of traps in gate insulator films. In this paper, we extract a large number of RTS data sets with large-scale array test patterns and evaluate the gate-bias voltage dependences of time constant ratio and amplitude. We demonstrate that the energy level of traps distributes uniformly at a drain current of at least 0.1–1.0 µA.

Statistical Evaluation of Process Damage Using an Arrayed Test Pattern in a Large Number of MOSFETs

Evaluating the statistical variations of MOSFETs is important for realizing accurate analog circuits and large-scale-integration devices. A new evaluation method for the statistical variation of the electrical characteristics of MOSFETs is presented. We have developed a test circuit for understanding the statistical and local variations of MOSFETs in a very short time. We demonstrate that the electrical characteristics in more than one million MOSFETs, such as the threshold voltage and the subthreshold swing (S-Factor), are measured in 30 min and that the measured results are very efficient in developing the fabrication process, the process equipment, and the device structure to reduce the statistical and local characteristic variation.

A 1.6mm 2 4,096 logic elements multi-context FPGA core in 90nm CMOS

In this paper, we propose a dynamically reconfigurable multi-context FPGA core named Flexible Processor IV (FP4). FP4 contains 16 times 16 physical logic elements (LE) and 16 context memory planes, thus virtually 4,096 LEs are available in total. The core size is only 1.36 mm times 1.15 mm in 90 nm CMOS technology. A critical issue of FP4 is to prevent the fall of multi-context execution speed. Therefore we have developed a shift-register-type temporal communication module (SR-TCM) and a design automation software named PELOC. PELOC can divide a circuit larger than the physical capacity of FP4 to several smaller sub-circuits while maintaining critical path delay equal among all the sub-circuits. By using the SR-TCM and PELOC, we confirmed that the execution speed of FP4 is almost constant regardless of the number of contexts used.

Ultra-low series resistance W/ErSi 2 /n + -Si and W/Pd 2 Si/p + -Si S/D electrodes for advanced CMOS platform

A formation technology of ultra-low series resistance CMOS source/drain (S/D) electrodes is developed. The silicide/silicon contact resistivity (R<inf>c</inf>) of 8.0×10⁻¹⁰ Ω·cm² and the electrodes sheet resistance (R<inf>sheet</inf>) of less than 5.0 Ω/□ are achieved for both n- and pMOS using W/ErSi<inf>2</inf> and W/Pd<inf>2</inf>Si metal stacked silicide structures. For the first time, FD-SOI CMOS with the developed S/D electrodes was fabricated and the ring oscillator speed performance was evaluated.

An image recognition processor using dynamically reconfigurable ALU

An image recognition processor, utilizing a phase only correlation (POC) algorithm is proposed. The arithmetic logical unit (ALU) in this processor can be re-configured dynamically. By arranging the POC algorithm to a form suitable for reconfigurable computing, the proposed processor can perform 2D 512/spl times/512 pixel image recognition within 105.2 ms and using 310.9 mW of power. This power consumption is 11.3 times lower than that of a previously reported work with same execution time.

A Fine-Grained Programmable Logic Module with Small Amount of Configuration Data for Dynamically Reconfigurable Field-Programmable Gate Array

Dynamically customizable and reconfigurable hardware architecture for a specific task on demand is one of the most important issues to bring out a novel-computing paradigm in the era of system LSIs. Our target is to realize a flexible processor which is a kind of dynamically reconfigurable field-programmable gate array (FPGA) and is able to execute signal processing while reading the next configuration data (CD) simultaneously. In order to realize the flexible processor, since the amount of CD is enormous in conventional FPGAs, it is necessary to reduce the amount of CD as much as possible. In this paper, we propose a newly developed programmable logic module that can reduce the amount of CD to no less than 86% of that for the conventional Look Up Table (LUT)-based programmable logic module.

Stress-induced leakage current and random telegraph signal

Stress-induced leakage current (SILC) and random telegraph signal (RTS) in n-type metal-oxide-semiconductor field-effect-transistor (n-MOSFETs) caused by the Fowler-Nordheim tunneling stress are studied by using the author’s newly developed test pattern. MOSFETs having large RTS increase can be induced by electrical stress in parallel with the inducing of SILC. Generation and recovery characteristics of SILC and RTS against the stress time and measurement temperature are very similar. However, the MOSFETs having large RTS are not related to ones having large anomalous SILC in this study. We consider that the traps that cause the RTS and anomalous SILC are the same, but their locations in SiO2 are different.