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Featured researches published by Naoto Ueda.


electronic components and technology conference | 2001

Thermo-electromigration phenomenon of solder bump, leading to flip-chip devices with 5,000 bumps

Kazuyuki Nakagawa; Shinji Baba; Masaki Watanabe; Hironori Matsushima; Kozo Harada; Eiji Hayashi; Qiang Wu; Akira Maeda; Makoto Nakanishi; Naoto Ueda

High performance logic devices have rapidly advanced in network system. In order to reply the demand of high pin count and high speed, Flip-chip BGA (FC-BGA) package applied high-density organic substrate has been developed. This package has the superior possibility of flexible bump locations by virtue of high via densities and fine line capabilities of the substrate. The feature of substrate is adopting the stacked method of finer via pitch layers. Utilizing the density, it is possible to either minimize the LSI die size or maximize the number of bumps on the die. Also at the high performance devices, the high current density through the bump is strongly demanded. In order to satisfy the demand and realize the high pin counts devices, thermo-electromigration phenomenon of solder bump is one of the key reliability items. The thermo-electromigration phenomenon of solder bump was investigated to be consisting of three steps as below. At 1/sup st/ step, the lead (Pb) migrates as electron flow under high-density current, and at 2/sup nd/ step, the Under Bump Metals (UBM) migrates and disappears. Finally at 3/sup rd/ step, Aluminum (Al) routing metal migrates and it results in open failure, and from the High Temperature Operating Life (HTOL) results, the life time of solder bump on current density has been estimated theoretically based on Blacks equation. The lifetime was predicted more than 20 years with the current being 160 mA/bump in 220 /spl mu/m pitch cases.


Archive | 1992

Solder material, junctioning method, junction material, and semiconductor device

Shunichi Abe; Katunori Asai; Yoshihiro Tomita; Hideyuki Ichiyama; Seizou Ohumae; Yoshirou Nishinaka; Katsuyuki Fukutome; Naoto Ueda; Toshio Takeuchi


electronic components and technology conference | 1996

Molded chip scale package for high pin count

Shinji Baba; Yoshihiro Tomita; Mitsuyasu Matsuo; Hironori Matsushima; Naoto Ueda; Osamu Nakagawa


Archive | 2000

Multilayer wiring base and method for manufacturing the same

Hirofumi Fujioka; Yasumichi Hatanaka; Toshihiro Iwasaki; Michitaka Kimura; Kazuhiro Tada; Naoto Ueda; Satoshi Yamada; 直人 上田; 和弘 多田; 聡 山田; 俊寛 岩崎; 通孝 木村; 康道 畑中; 弘文 藤岡


名古屋大学附属図書館研究年報 | 2008

わが国の大学図書館におけるラーニング・コモンズの事例研究 (特集 ラーニング・コモンズ)

直人 上田; 豊祐 長谷川; Naoto Ueda; Toyohiro Hasegawa


Journal of Japan Institute of Electronics Packaging | 1995

Chip Scale Package

Shinji Baba; Naoto Ueda; Osamu Nakagawa


Archive | 1993

A method of manufacturing a semiconductor device having the LOC structure, as well as related lead wire frame

Yoshihiro Tomita; Naoto Ueda; Yoshirou Nishinaka; Shunichi Abe; Hideyuki Ichiyama


Archive | 1993

Halbleitervorrichtung mit LOC-Struktur sowie dazugehöriges Herstellungsverfahren und dazugehöriger Zuführungsdraht-Rahmen

Yoshihiro Tomita; Naoto Ueda; Yoshirou Nishinaka; Shunichi Abe; Hideyuki Ichiyama


Archive | 1993

Zuführungsdraht-Rahmen zur Verwendung bei der Herstellung einer Halbleitervorrichtung mit LOC-Struktur und Verfahren zur Herstellung einer Halbleitervorrichtung mit LOC-Struktur A lead wire frame for use in the manufacture of a semiconductor device having the LOC structure and method of manufacturing a semiconductor device having the LOC structure

Yoshihiro Tomita; Naoto Ueda; Yoshirou Nishinaka; Shunichi Abe; Hideyuki Ichiyama


Archive | 1993

Verfahren zur Herstellung einer Halbleitervorrichtung mit LOC-Struktur sowie dazugehöriger Zuführungsdrahtrahmen A method of manufacturing a semiconductor device having the LOC structure, as well as related lead wire frame

Yoshihiro Tomita; Naoto Ueda; Yoshirou Nishinaka; Shunichi Abe; Hideyuki Ichiyama

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