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electronic components and technology conference | 1996

Molded chip scale package for high pin count

Shinji Baba; Yoshihiro Tomita; Mitsuyasu Matsuo; Hironori Matsushima; Naoto Ueda; Osamu Nakagawa

A unique molded chip scale package (CSP) associated 1024 pin counts has been developed. This package has the bare die soldering feature, that means highest mount density and enhanced electrical characteristic, and the robust package feature, that means easy to handle, to test and to standardize such as known good die (KGD). The wiring conductor patterns made of copper realized enhanced electrical characteristic. The solder bumping process with screen printing technique, was applied with cost competitiveness. And the transfer molding process produced high reliable package.


electronic components and technology conference | 1998

Thermally enhanced flip-chip BGA with organic substrate

Hironori Matsushima; Shinji Baba; Yoshihiro Tomita; M. Watanabe; E. Hayashi; Y. Takemoto

A thermally enhanced Flip-chip BGA package (FC-BGA) with organic substrate has been developed. The package is proud of the high thermal and electrical performance due to the flip-chip interconnections, and the optimized heat spreader attached directly on to the die. Besides, the eutectic solder bumps (Pb63wt% Sn) have realized high reliability of flip-chip interconnections, compared with the high melting point solder bumps (Pb-3wt% Sn connected with Pb-63wt% Sn).


electronic components and technology conference | 1999

Flip-chip BGA applied high-density organic substrate

Shinji Baba; Qiang Wu; E. Hayashi; M. Watanabe; Hironori Matsushima; Yoshihiro Tomita; Y. Takemoto

In the area of high-end logic devices, high pin counts, high speed and high thermal dissipation are strongly required for packages. A Flip-Chip BGA (FC-BGA) has been developed for such requirements. The FC-BGA has successfully realized up to 1681 pin counts and lower crosstalk noise, by using a high-density organic substrate with the 30 /spl mu/m/30 /spl mu/m line and spacing width rule and optimizing the substrate layer structure. Furthermore, in order to realize a highly reliable package, the Under Bump Metal (UBM) made of Ni/Cu/Ti for eutectic solder bump was developed and the flux-less bonding process was introduced. The FC-BGA packages applied high-density organic substrate has been developed for leading edge logic devices of networking and computing systems.


Archive | 1992

Solder material, junctioning method, junction material, and semiconductor device

Shunichi Abe; Katunori Asai; Yoshihiro Tomita; Hideyuki Ichiyama; Seizou Ohumae; Yoshirou Nishinaka; Katsuyuki Fukutome; Naoto Ueda; Toshio Takeuchi


Archive | 2004

Method of manufacturing a solid state image sensing device

Kenji Hanada; Masaki Nakanishi; Kunio Shigemura; Takaomi Nishi; Koji Shida; Izumi Tezuka; Shunichi Abe; Yoshihiro Tomita; Mitsuaki Seino; Tohru Komatsu


Archive | 2002

Lamination packaging method of semiconductor chip

Masaki Tago; Yoshihiro Tomita; 至洋 冨田; 雅基 田子


Archive | 2003

LAMINATED LAYER TYPE SEMICONDUCTOR DEVICE

Hirofumi Fujioka; Hiroshi Fukumoto; Yoshihiro Tomita; Naoki Yuya; 至洋 冨田; 直毅 油谷; 宏 福本; 弘文 藤岡


Archive | 1992

METHOD FOR BONDING SEMICONDUCTOR ELEMENT

Katsunori Asai; Hideyuki Ichiyama; Seizo Omae; Yoshihiro Tomita; 秀之 一山; 至洋 冨田; 誠蔵 大前; 勝乗 浅井


Archive | 1999

MOUNTING STRUCTURE AND MOUNTING METHOD FOR SEMICONDUCTOR DEVICE

Yoshihiro Tomita; 至洋 冨田


Archive | 2003

SEMICONDUCTOR HIGH FREQUENCY DEVICE AND MANUFACTURING METHOD THEREFOR

Tatsuya Fukami; Tamotsu Nishino; Yoshihiro Tomita; Yukihisa Yoshida; 至洋 冨田; 幸久 吉田; 達也 深見; 有 西野

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