Naoya Suzuki

Large Panel Level Fan Out Package Built up Study with Film Type Encapsulation Material

Die first and face up type FO-PLP preparation was studied referring the organic substrate fabrication process. 660 mm x 515 mm size carrier was used and 640 mm x 495 mm area was encapsulated with the film molding material comparing with granule material. 3 mm x 3mm to 10 mm x 10 mm dies were mounted on the panel using temporary adhesive. Die shift at compression molding was evaluated in each die size. Larger die showed smaller die shift distance. The affection of the carrier CTE to the die shift was also investigated. The board which had CTEs of 6, 8, and 14 ppm/K were used. CTE of 14 ppm/K material showed the minimum di shift. Tracking of the warpage during the preparation process by each process step indicated that each material selection can control the warpage. Wiring layer was fabricated on the die molded panel which had the size of 510 mm x 407 mm. Laminate type insulation material was used. Filled via of 35 micron diameter and L/S = 15 / 15 micron was formed by 355 nm laser drilling and SAP.

Warpage study of FO-WLP build up by material properties and process

Warpage issue of the complex structure of fan-out wafer level package was studied and the suitable mechanical model was obtained. By using the model, the warpage in 12-inch wafer can be reduced within 2 mm, both after post mold cure and grinding of molding compound by optimizing the mechanical properties.

Compensation of Surface Roughness Using an Au Intermediate Layer in a Cu Direct Bonding Process

Copper-copper (Cu-Cu) direct bonding assisted by direct immersion gold (DIG) was demonstrated. Cu-Cu direct bonding is a critical technology for inductively coupled memory interconnections. To solve the problems of conventional methods of Cu-Cu direct bonding, a plating process using DIG to form an intermediate layer was selected. The concept of the developed bonding process is to use deformation of DIG to compensate for the surface roughness of the Cu substrates during application of pressure and annealing. Using this method, precise surface flattening of Cu substrates is not necessary. Bonding can be achieved even in an air atmosphere. A sample bonded at a temperature of 350°C failed within the chip in a shear test. It was found that bonding can be achieved when the gold (Au) thickness is greater than the half of the surface roughness of Cu at the bonding temperature. Transmission electron microscopy-energy-dispersive x-ray spectroscopy revealed that Au diffused into Cu during bonding. The diffusion constant of Au into Cu was investigated through a numerical calculation. The obtained results showed good agreement with the literature values.

Study of influence of mechanical property of temporary bonding adhesive on warpage of FO-WLP

Warpage suppression of FO-WLP during the fabrication process on the support was studied in the view point of material properties of temporally adhesive. It was found that Youngs modulus of the temporally bonding adhesive influenced the warpage significantly and using that of small Youngs modulus could suppress the warpage.

Study of influence of under-fill matetrial properties on the reliability of FC-BGA

The dependence of the strain around solder joint on underfill material properties was studied using three different materials by both of the simulation and the experimental measurement. The internal strain of the underfill during the temperature cycle which is −55 to 125°C was monitored. The temperature cycle test up to 1000 times was also implemented with the daisy chain open / short test of the solder joints. To reduce the strain of solder joint and the stress around solder joint, it is important to optimize the underfill properties, especially glass transition temperature and Youngs modulus.

Expanding Film and Process for High Efficiency 5 Sides Protection and FO-WLP Fabrication

The novel expanding film and the process have been developed for the fabrication of 5 sides protection of die and fan out wafer level package. This can skip the time-consuming die-replacement process for die gap widening. The process consists of the steps of expanding of diced-wafer on the film, transferring the dice to the carrier, over-molding and mold dicing. Every die edge protection by molding compound and the singulation was demonstrated. The die gap was able to be controlled from 0.5 mm to 3.5 mm. In the case of 1.5 mm die gap, the standard deviation was about 0.05 mm. It was also indicated that the film could be applied for 1 mm × 1 mm, 5 mm × 5 mm and 10 mm × 10 mm size dice.

Development and Evaluation of Carrier Glass Substrate for Fan-Out WLP/PLP Process

The effect of glass type used as fan-out carrier substrate on the reliability of the electrical devices were investigated. Glasses with thermal expansion coefficient of around 6~8 ppm/K with and without alkali ions involved in the glass were tested. With using non-alkali type glass as the carrier material, it was confirmed that the lifetime of the test vehicles were longer than that heated with conventional soda-lime silicate glass by the evaluation under highly accelerated steam and temperature condition.

Warpage Suppression during FO-WLP Fabrication Process

Composing material combination of the re-distribution layer first type fan out wafer level package with various die occupancy ratio during the fabrication process on the support was studied by both of the making test vehicle and the numerical simulation. The investigated TV composed of glass support, temporary bonding adhesive, 1st re-distribution dielectric layer, Cu layer, 2nd re-distribution dielectric layer, Si die with die attached adhesive and molding compound. The fabrication was performed by the steps of applying all the materials serially and the final step of grinding down of the mold surface. The die occupation ratio in the TV become larger, the warpage of the TV decreased. The CTE of the support influenced the TV warpage significantly comparing with the CTEs of the EMC, the RDL dielectric layer and the TBA. From the investigated results the strategy of the appropriate selection of the materials to the die occupation factor was made to know. It suggested that the die occupation ratios were 21, 40 and 66%, using the support with the CTE of about 8, 10, 11 x10-6/°C and the EMC with the CTE of 8.4 x10-6/°C could make non warped TV, respectively. It was also suggested that the warpage could be controlled within 1mm during all the fabrication process steps by using the support with the CTE of 8.0 to 8.7 x10-6/°C in case of that the die occupation ratio was 40% and the CTE of EMC was 8.4 x10-6/°C.

Cu-Cu direct bonding by introducing Au intermediate layer

Cu-Cu direct bonding under help of direct immersion gold (DIG) for multi-die fan-out wafer level package was demonstrated. Cu-Cu direct bonding is a critical technology for high-frequency applications. To solve challenges of conventional methods, the DIG was used. As a result, a cohesion failure was obtained in shear test.

Study on prediction about residual position of void generated by resin flow

Liquid epoxy resin is used in various types of mobile information equipment and devices and expected to be a key material for flip chip packaging [1-2]. The flip chip connection process is a thermo-compression molding process. In this process, air voids may remain behind due to the bump shape and resin properties; therefore, an appropriate molding condition is necessary. We developed a computer-aided engineering (CAE) technique to calculate the generation of air voids and flow of resin and evaluated it in terms of prediction about the position of residual voids. This technique involves global resin-and-particle coupled moving and local air-resin two-phase flow analyses. In this paper, we give an example of prediction about the position of residual voids generated by resin flow by using our CAE technique. By clarifying the molding phenomena through analysis, we clarified the material properties suitable for a molding process.