Narain D. Arora

Modeling and characterization of copper interconnects for SoC design

Interconnect (wiring) is central to nanometer system-on-a-chip (SoC) design. As such, accurate interconnect modeling and characterization are key to the design and verification of SoCs. Today copper (Cu) has become a mainstream material for on-chip interconnections. Unlike aluminum (Al) interconnects, Cu wire line width and thickness is a function of wire width and spacing, wire-pattern density, and topography. These new effects must be modeled accurately for designs to achieve first-time silicon success. In this paper, we discusses the Cu process and its impact on modeling the interconnect parasitic elements - resistance (R), capacitance (C), and inductance (L). For a given process node, the use of Cu reduces interconnect delay and power, but from a design prospective, the same effect is achieved by reducing wire length. The impact of the X-architecture, which makes pervasive use of diagonal lines and has the promise of reducing wire length by an average of 20%, is also discussed. Finally, silicon validation of the interconnect R, C, and L model, using a test-chip approach, is covered.

Interconnect characterization of X architecture diagonal lines for VLSI design

This paper addresses the manufacturability, yield, and reliability aspects of X Architecture interconnects (diagonal lines) in a very large scale integrated (VLSI) design that enables integrated circuit (IC) chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130- and 90-nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line, and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance, and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan versus X Architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X Architecture designs.

Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design

This paper deals with the measurement and modeling of on-chip interconnect inductance in a VLSI chip fabricated using a sub-100 nm copper (Cu) CMOS process. A test chip was designed and fabricated in a 90 nm process node, to study the inductive effects, with various inductive return paths, including substrate, co-planar structures, power grids, and random structures. S parameter measurements were made on these structures to extract wire inductance and skin effect. It was observed that the presence of CMP dummy metal fills influences the inductive behavior and skin effect of the Cu process. Inductive effects for Cu interconnects are then compared with previous studies on aluminum (Al) interconnect at 130 nm. This is followed by a discussion on the significance of inductance effects in sub-100 nm X architecture chip design.

Test chip characterization of X architecture diagonal lines for SoC design

This paper addresses the manufacturability, yield and reliability aspects of an X architecture (diagonal lines) silicon-on-chip (SoC) design that enables IC chips to become faster and smaller (area) compared to the same design in a Manhattan structure. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both a 130 nm and a 90 nm copper CMOS processes. The measurements of the line resistance (Kelvin structures), capacitance (inter-digited structure) and SEM data show that for 1:1 design rules (Manhattan vs. X architecture), the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, and wafer processing techniques are applicable to X architecture designs.

On-Chip Inductance in X Architecture Enabled Design

The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition times. The accurate modeling of inductance behavior is thus essential for high speed VLSI designs. Recently X architecture has been introduced to reduce overall IC interconnect length by using diagonal wirings pervasively, resulting in smaller die sizes and higher performance. Although the resistance and capacitance of diagonal wires and their modeling are well understood, the characterization and modeling studies of diagonal wire inductance remain scarce. In this paper, the authors study the inductance effects of diagonal wiring, specifically inductance with return loop through diagonal (X Architecture) and Manhattan power grids. Both self and mutual inductance of Manhattan and diagonal wirings in the presence of various power grids are obtained using both FastHenry simulations and on-chip measurements. Results show that both self and mutual inductance values of diagonal signal line(s) are invariant with respect to their placement relative to the power grid. We observe that measurements done on an actual test chip agree fairly well with simulation data. This makes inductance modeling in X Architecture designs easier compared to Manhattan design, and X Architecture design has an advantage over Manhattan design from inductance perspective

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

The X Architecture offers the potential to produce smaller and faster integrated circuits through the pervasive use of 45° wirings on the upper metal layers. The X Initiative members have demonstrated its manufacturability and integration-worthiness at the 130nm, 90nm and 65nm process technology nodes. This paper explores the use of off-axis lithography illumination to print 45° diagonal wires at leading technology nodes. The paper also describes the RET strategies employed for the X Architecture and the effectiveness of various illumination sources at various process nodes. Process window and metal wiring CD variation of Manhattan and X Architecture are compared in the simulations using different types of illuminators. Simulation shows that using 193nm light source, Manhattan and X designs can easily be printed with different types of illuminating source in either 90nm or 65nm process node. Silicon test chips at 90nm that include typical X routing patterns are designed to verify the printability of X Architecture wirings. Electrical measurements as well as SEM analysis are conducted and results show that the fidelity of diagonal wirings is as good as traditional Manhattan routings.

Manufacturability of the X Architecture at the 90-nm technology node

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.

Taking the X Architecture to the 65-nm technology node

The X Architecture is a new way of orienting the interconnect on an integrated circuit using diagonal pathways, as well as the traditional right-angle, or Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, the X Architecture can provide substantial improvements in chip performance, power consumption and cost. Members of the X Initiative semiconductor supply chain consortium have demonstrated the production worthiness of the X Architecture at the 130-nm and 90-nm process technology nodes. This paper presents an assessment of the manufacturing readiness of the X Architecture for the 65-nm technology node. The extent to which current production capabilities in mask writing, lithography, wafer processing, inspection and metrology can be used is discussed using the results from a 65-nm test chip. The project was a collaborative effort amongst a number of companies in the IC fabrication supply chain. Applied Materials fabricated the 65-nm X Architecture test chip at its Maydan Technology Center and leveraged the technology of other X Initiative members. Cadence Design Systems provided the test structure design and chip validation tools, Dai Nippon Printing produced the masks and Canon’s imaging system was employed for the photolithography.