Narendra Parihar

A Modeling Framework for NBTI Degradation Under Dynamic Voltage and Frequency Scaling

A modeling framework is proposed to predict the degradation and recovery of threshold voltage shift (ΔV_T) due to negative bias temperature instability. Double interface reaction- diffusion model with transient trap occupancy model is used to predict the generation and recovery of interface traps (ΔV_IT). Empirical stretched exponential equations are used to capture hole trapping and detrapping in preexisting traps (ΔV_HT). The framework consists of uncoupled contributions from ΔV_IT and ΔV_HT and is capable of accurately predicting the ultrafast measured ΔV_T during dc, arbitrary multicycle dc, ac, and mixed-mode dc-ac stress. It can predict pulse duty cycle and frequency dependence of ac degradation and also dynamic voltage and frequency scaling waveforms encountered in actual circuits.

Aging-aware voltage scaling

As feature sizes of transistors began to approach atomic levels, aging effects have become one of major concerns when it comes to reliability. Recently, aging effects have become a subject to voltage scaling as the latter entered the sub-μs regime. Hence, aging shifted from a sole long-term (as treated by state-of-the-art) to a short and long-term reliability challenge. This paper interrelates both aging and voltage scaling to explore and quantify for the first time the short-term effects of aging. We propose “aging-awareness” with respect to voltage scaling which is indispensable to sustain runtime reliability. Otherwise, transient errors, caused by the short-term effects of aging, may occur. Compared to state-of-the-art, our aging-aware voltage scaling optimizes for both short-term and long-term aging effects at marginal guardband overhead.

Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Negative Bias Temperature Instability (NBTI) is due to interface trap generation (ΔN<inf>it</inf>) and trapping of holes in gate insulator traps (ΔN<inf>It</inf>). However, the isolation methods and the relative dominance of ΔN<inf>it</inf> and ΔN<inf>it</inf>, time constants of ΔN<inf>it</inf> and ΔN<inf>it</inf> for stress, recovery and associated temperature (T) activation, and whether ΔN<inf>it</inf> recovers or remains permanent after stress, are widely debated. The resolution of such disputes is necessary to develop a reliable NBTI model. This work uses carefully designed measurements and simulations to resolve the aforementioned disputes. The contribution of ΔN<inf>it</inf> and ΔN<inf>it</inf> on overall threshold voltage shift (ΔN<inf>t</inf>) is determined. Kinetics of ΔN<inf>it</inf> and ΔN<inf>it</inf> during stress and recovery, T activation and associated time constants are verified in both large and small area devices. Existing theoretical models for ΔN<inf>it</inf> and ΔN<inf>it</inf> are benchmarked and validated against DC and AC experiments. Capability of the existing models for predicting end-of-life ΔN<inf>t</inf> is demonstrated.

Consistency of the Two Component Composite Modeling Framework for NBTI in Large and Small Area p-MOSFETs

Consistency of the recently proposed deterministic composite modeling framework for Negative Bias Temperature Instability (NBTI) in large area devices is verified for stochastic NBTI in small area devices. The framework has two independent and uncoupled components, interface trap generation (ΔV_IT), and hole trapping in pre-existing defects (ΔV_HT). The time evolution of mean threshold voltage shift (ΔV _T), from multiple ultra-fast measurements in small area devices under diverse stress and recovery conditions, is predicted by the deterministic composite framework. It is shown that although the physical mechanism of NBTI remains the same as the device area is scaled, there can be significant differences in the relative ΔV_IT and Δ V_HT contribution to ΔV_T between large and small area devices, which can alter the overall model parameters. A stochastic simulation framework, fully consistent with the deterministic framework, is developed, which is shown to predict experimentally measured mean time evolution of ΔV_T in small area devices.

Comparison of DC and AC NBTI kinetics in RMG Si and SiGe p-FinFETs

An ultrafast characterization method is used to study DC and AC NBTI in Si and SiGe channel core RMG p-FinFETs. The time evolution of degradation during and after stress, and the impact of stress bias, temperature, frequency and duty cycle are characterized. A physics-based model is used to qualitatively explain measured data. The similarities and differences of DC and AC NBTI in Si and SiGe channel devices are highlighted.

Predictive TCAD for NBTI stress-recovery in various device architectures and channel materials

A 3-D TCAD framework is proposed for simulating Negative Bias Temperature Instability (NBTI) in Silicon (Si) and Silicon Germanium (SiGe) channel p-MOSFETs. Different types of device architectures such as planar, bulk and SOI FinFETs as well as Gate All Around Nanowire FETs (GAA NWFETs) have been simulated. The framework can predict device degradation during stress and the recovery of degradation after stress. NBTI measured data are predicted for Si and SiGe planar devices with different Ge%, and Si FinFETs. Calibrated TCAD is used to predict impact of technology scaling on NBTI, for constant gate bias (VG) and constant overdrive (VOV) stress. It is reported that (1) reducing the fin and NW width makes NBTI reliability worse for FinFETs and NWFETs, (2) devices with SiGe channel offer superior NBTI reliability as compared to Si channel, consistent with published reports, and (3) GAA NWFETs are more NBTI-prone when compared to planar and FinFET architectures. The fin and NW geometry dependence of NBTI Voltage Acceleration Factor (VAF) and degradation at End-Of-Life (EOL) have been investigated in detail.

A review of NBTI mechanisms and models

Abstract A comprehensive review is done of different NBTI mechanisms and models proposed in the literature over the past years. The Reaction-Diffusion (RD) model based comprehensive framework and the alternative Energy Well (EW) models are discussed. The model capabilities to simultaneously predict the temporal kinetics of stress and recovery are evaluated. Key experimental signatures that support or refute model assumptions are highlighted.

A BTI analysis tool (BAT) to simulate p-MOSFET ageing under diverse experimental conditions

A physical modeling framework is demonstrated for Negative Bias Temperature Instability (NBTI). It can simulate temporal kinetics of threshold voltage shift (ΔVt) during and after DC and AC stress and mixed DC-AC stress for dynamic voltage, frequency and activity conditions. It can predict gate insulator process dependence and is consistent with large and small area devices. The framework is included in a commercial TCAD software to simulate degradation of FinFETs and GAA NWFETs.