Nilesh Goel

A Comparative Study of Different Physics-Based NBTI Models

Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

A consistent physical framework for N and P BTI in HKMG MOSFETs

A common framework of trap generation and trapping is used to explain Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) DC and AC stress/recovery data. NBTI is explained using trap generation in Si/SiON (IL) interface and SiON (IL) bulk, together with hole trapping in pre-existing bulk SiON (IL) traps. Interface trap generation and recovery can be fully explained using Reaction-Diffusion (RD) model. PBTI is explained using trap generation in SiON (IL)/HK interface and HK bulk, together with electron trapping in pre-existing bulk HK traps. Important similarities as well as differences between N and P BTI are highlighted.

A comprehensive AC / DC NBTI model: Stress, recovery, frequency, duty cycle and process dependence

A comprehensive NBTI framework using the H/H2 RD model for interface traps and 2 well model for hole traps has been proposed and used to predict DC and AC experiments. The framework is validated against experimental data from different DC stress and recovery conditions, AC frequency and duty cycle, measurement speed, and across SiON and HKMG devices having different gate insulator processes. Limitations of the alternative 2 stage model framework is discussed.

A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs

Abstract A comprehensive modeling framework involving mutually uncorrelated contribution from interface trap generation and hole trapping in pre-existing, process related gate insulator traps is used to study NBTI degradation in SiON and HKMG p-MOSFETs. The model can predict time evolution of degradation during DC and AC stress, time evolution of recovery after stress, impact of stress and recovery bias and temperature, and impact of several AC stress parameters such as pulse frequency, duty cycle, duration of last pulse cycle (half or full) and pulse low bias. The model can successfully explain experimental data measured using fast and ultra-fast methods in SiON and HKMG devices having different gate insulator processes. The trap generation and trapping sub components of the composite model have been verified by independent experiments. Data published by different groups are reconciled and explained. The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices.

A Modeling Framework for NBTI Degradation Under Dynamic Voltage and Frequency Scaling

A modeling framework is proposed to predict the degradation and recovery of threshold voltage shift (ΔV_T) due to negative bias temperature instability. Double interface reaction- diffusion model with transient trap occupancy model is used to predict the generation and recovery of interface traps (ΔV_IT). Empirical stretched exponential equations are used to capture hole trapping and detrapping in preexisting traps (ΔV_HT). The framework consists of uncoupled contributions from ΔV_IT and ΔV_HT and is capable of accurately predicting the ultrafast measured ΔV_T during dc, arbitrary multicycle dc, ac, and mixed-mode dc-ac stress. It can predict pulse duty cycle and frequency dependence of ac degradation and also dynamic voltage and frequency scaling waveforms encountered in actual circuits.

Combined trap generation and transient trap occupancy model for time evolution of NBTI during DC multi-cycle and AC stress

A transient trap occupancy model is proposed to determine the charged state of generated N_IT in real time during successive stress (pulse ON) and recovery (pulse OFF) cycles for DC and AC NBTI stress. The model converts ΔN_IT (trap density) to compute the ΔV_IT (voltage shift) subcomponent of overall ΔV_T; time evolution of ΔN_IT is obtained using numerical RD simulation for multi-cycle DC and low f AC, and a calibrated compact model for high f AC stress to reduce simulation time. A cyclostationary stretched exponential model is used for the ΔV_HT subcomponent of ΔV_T. The complete model is used to predict time evolution of ΔV_T (=ΔV_IT + ΔV_HT), measured using Ultra-Fast MSM method in HKMG p-MOSFETs for multiple and completely arbitrary DC stress and recovery cycles and for AC stress at different duty, f and pulse low bias. Finally a compact model is proposed, which is capable of providing AC/DC ratio at fixed time and compared to the transient model for different gate activity.

A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

DC and AC NBTI in deep EOT scaled HKMG p-MOSFETs with different IL (scaled to sub 2Å) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔV_IT-IL) at Si/IL interface, hole trapping (ΔV_HT) in IL bulk and trap generation (ΔV_IT-HK) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict V_T shift (ΔV_T) during and after DC stress, dependence on pulse duty cycle (PDC) and frequency (f) for AC stress, and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied, and end-of-life degradation has been estimated.

Investigation of stochastic implementation of reaction diffusion (RD) models for NBTI related interface trap generation

Conventional H/H2 and poly H/H2 Reaction-Diffusion (RD) models are compared, and the poly version is explored as a more physically likely model for predicting interface trap (NIT) generation during Negative Bias Temperature Instability (NBTI) in p-MOSFETs. Stochastic implementations of the conventional H/H2 RD model and the poly H/H2 RD model are realized, and their equivalence to continuum implementations are investigated for large area devices. Impact of dimensionality (1D, 2D, 3D) and device size (W, L) are explored for stochastic implementation. Stochastic simulations for small area devices using the poly H/H2 RD model show long term 1/6 power law time exponent during stress. A comprehensive framework consisting of H/H2 RD model for NIT along with empirical models for hole trapping (NHT) and bulk trap generation (NOT) is able to predict experimental data for a wide variety of large area devices for different experimental conditions. Variation of small area device degradation has been simulated and compared to experimental results.

Trap Generation in IL and HK layers during BTI / TDDB stress in scaled HKMG N and P MOSFETs

Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for NBTI is attributed to Si/IL and IL/HK interfaces; TG from DCIV for PBTI to IL/HK interface but at similar energy location as NBTI. TG from DCIV shows similar stress bias (VG,STR), time (tSTR) and temperature (T) dependence for NBTI and PBTI, while TG for PBTI from SILC shows very different dependence as it likely scans TG at different spatial and energetic locations. TG contribution to VT shift (ΔVT) is compared to ΔVT from ultra-fast measurements. A compact model is used to predict overall BTI ΔVT considering uncorrelated contributions from independently measured TG and trapping (TP) in pre-existing and generated bulk traps. Impact of IL scaling on BTI and its underlying subcomponents are studied. Physical origins of different TG and TP processes have been identified using Density Functional Theory (DFT) simulations.

Ultrafast AC–DC NBTI Characterization of Deep IL Scaled HKMG p-MOSFETs

Ultrafast DC and AC negative bias temperature instability (NBTI) measurements are done in high-k metal gate p-MOSFETs having deeply scaled interlayer. Time evolution of degradation during and after DC and AC stress at different duty cycle and frequency are characterized. Impact of last pulse cycle duration (half or full) and pulse low bias on AC stress are studied. Equivalence of measured data from large and small area devices are shown. Experimental results are qualitatively explained using known NBTI physical mechanism.