Narinderjit Singh

Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as well. The need to transform the conventional logic gates into modified ones having the same functionality but are highly noise-tolerant is catered by the technique Markov Random Field (MRF) modelling proposed in [1]. This paper contributes towards explaining MRF design in a simplified form, proves the error tolerant capability of MRF circuits by simulations performed in Cadence (simulation software) and finally proposes an improvement in the design of [1].

Sensitivity analysis of Probability Transfer Matrix (PTM) on same functionality circuit architectures

As CMOS technology advances to nano-scale devices, the performance of logic integrated circuits becomes a focal point in current literatures. The circuits performance measured based on its reliability is not only depending on its gate error probability, p, but it also depends on the architecture of that circuit. Thus, this drives a need to measure and evaluate reliability values for different architectures of same functionality circuit. This paper looks into the performance comparison in terms of reliability measurement for different architectures of same functionality circuits using common reliability evaluation models such as Probabilistic Gate Model (PGM), Boolean Difference-based Error Calculator (BDEC) and Probabilistic Transfer Matrix (PTM). For this purpose, we have chosen C17 and Full Adder as our benchmark test circuits. It has been shown that only PTM model is able to evaluate reliability values for different architectures of C17 and Full Adder circuits whereas PGM and BDEC models depict no change in their reliability values. Simulation results conclude that PTM model has the ability to show its sensitivity to reliability measurement for different circuit architectures of same functionality circuits compared to PGM and BDEC. PTM sensitivity analysis is necessarily significant to circuit designers in producing robust and more reliable nano-scale circuit systems.

Computation and analysis of output error probability for C17 benchmark circuit using bayesian networks error modeling

The reliability of digital circuits is in question since the new scaled transistor technologies continue to emerge. The major factor deteriorating the circuit performance is the random and dynamic nature of errors encountered during its operation. Output-error probability is the direct measure of circuits reliability. Bayesian networks error modeling is the approach used to compute error probability of digital circuits. In our paper, we have used this technique to compute and analyze the output error probability of LGSynths C17 benchmark circuit. The simulations are based on MATLAB and show important relationships among output-error probability, execution time and number of priors involved in the analysis.

Joint and marginal probability analyses of Markov Random Field networks for digital logic circuits

With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit design. As a general overview of fault-tolerance, we start with comparing on-going techniques for fault-tolerant design. Later, we explain the two basic terminologies of MRF i.e. Joint and Marginal Probability followed by their computation for M3 module of C432 Interrupt Controller (as our test circuit). The contribution of this paper is the derivation of circuit design rules based on the conclusions obtained by these two probability analyses.

Evaluation of circuit reliability based on distribution of different signal input patterns

As digital logic circuit are being fabricated at nanometer scale, the reliability of the circuit becomes an important issue. Therefore the reliability modeling is increasingly important subject to be considered in designing modern logic integrated circuits at submicron level. This drives a need to compute reliability measure for nano-scale circuits. Two main reliability measuring tools used commonly in the literature are e.g. Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) other than Probabilistic Transfer Matrix (PTM). Here, the research work is constrained to PGM and BDEC models only as PTM model consume higher execution time and memory usage. This paper looks into the accuracy of circuits reliability evaluation by BDEC compared to control reliability evaluation method, PGM. Both models are able to estimate circuits reliability in the presence of soft errors. It is shown that BDEC model gives higher reliability values compared to PGM model for a set of circuits with same functionality but as the complexity of the circuits and the gate error values increases, BDEC tend to be inferior compared to PGM. This occurrence is explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure for BDEC depends on the circuit design (though with same functionality), gate error and probability of the input signal, being one or zero.

Accurate modeling method to evaluate reliability of nanoscale circuits

Reliability has become an important design consideration for integrated circuits especially as CMOS dimension enters into the nanoscale regime. An ability to accurately measure reliability of CMOS circuits has become very crucial. Tools such as Probabilistic Gate Model (PGM), Boolean Difference-based Error Calculator (BDEC) and Probabilistic Transfer Matrix (PTM) have been developed to measure reliability of a given circuit. However, there has not been work done to determine the efficiency of these tools in giving not only accurate but transparent reliability measure. In this work, a general computational technique based on statistical dependency of circuits input/output signals has been developed to validate the accurateness and correctness of the evaluation tools in computing reliability of selected benchmark test circuits. The computation is carried out by partitioning the benchmark test circuits. The reliability measures yield from these partitions are then evaluated for the selection of efficient tool. The statistical dependency-based method enables a simple yet competent way to conclude that PTM gives significantly adequate reliability measure compared to PGM and BDEC. Therefore, to obtain best circuit design with highest reliability measure, PTM modeling method would be the best consideration for reliability evaluation of nanoscale circuits.

Evaluating the effectiveness of digital storytelling with panoramic images to facilitate experience sharing

Technology advancement has now enabled experience sharing to happen in a digital storytelling environment that is facilitated through different delivery technologies such as panoramic images and virtual reality. However, panoramic images have not being fully explored and formally studied especially to assist experience sharing in digital storytelling setting. This research aims to study the effectiveness of an interactive digital storytelling to facilitate the sharing of experience. The interactive digital storytelling artifact was developed to convey the look and feel of Universiti Teknologi PETRONAS through the panoramic images. The effectiveness of digital storytelling through panoramic images was empirically tested based on the adapted Delone and McLean IS success model. The experiment was conducted on participants who have never visited the university. Six hypotheses were derived and experiment showed that there are correlations between user satisfaction of digital storytelling with panoramic images and users individual impact of the application to assist experience sharing among users. Hence, this research concludes a model on the production of an effective digital storytelling with panoramic images for specific experience sharing to bloom among users.

Improvement in reliability by changing the deterministic inputs of nanoscale circuits

Scaling of CMOS technology is degrading the reliability of upcoming microelectronic devices. When the circuit design enters the nanoscale dimensions, the inputs have more influence on the circuits reliability due to the circuits internal noises and gate errors. In this paper, we will model the deterministic inputs probabilistically and analyze their effect on the reliability of digital circuits. The analysis is based on the Bayesian networks error modelling scheme. The simulations are based on MATLAB and show the important relationships among different deterministic inputs and their reliabilities. The results show the range of reliability values obtained by changing the deterministic input probability values.

Programmed tool for quantifying reliability and its application in designing circuit systems

As CMOS technology scales down to nanotechnologies, reliability continues to be a decisive subject in the design entry of nanotechnology-based circuit systems. As a result, several computational methodologies have been proposed to evaluate reliability of those circuit systems. However, the process of computing reliability has become very time consuming and troublesome as the computational complexity grows exponentially with the dimension of circuit systems. Therefore, being able to speed up the task of reliability analysis is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into developing a MATLAB-based automated reliability tool by incorporating the generalized form of the existing computational approaches that can be found in the current literature. Secondly, a comparative study involving those existing computational approaches is carried out on a set of standard benchmark test circuits. Finally, the paper continues to find the exact error bound for individual faulty gates as it plays a significant role in the reliability of circuit systems.

Reliability Programmed Tool and its Application for Fault Tolerance Computation

With the continuous scaling of CMOS technology, reliability of nanobased electronic circuits is endlessly becoming a major concern. Due to this phenomenon, several computational approaches have been developed for the reliability assessment of modern logic integrated circuits. However, these analytical methodologies have a computational complexity that increases exponentially with the circuit dimension, making the whole reliability assessment process of large circuits becoming very time consuming and intractable. Therefore, to speed up the reliability assessment of large circuits, this paper firstly looks into the development of a programmed reliability tool. The Matlab-based tool is developed based on the generalization of Probabilistic Transfer Matrix (PTM) model as one of the existing reliability assessment approaches. Users have to provide description of the desired circuit in the form of Netlist that becomes the input to the programmed tool. For illustration purpose, in this paper, C17 has been used as the benchmark test circuit for its reliability computation. Secondly, reliability of a desired circuit does not only depend on its faulty gates, but it also depends on the maximum error threshold of these faulty gates above which no reliable computation is possible. For this purpose, the developed tool is employed again to find the exact error thresholds for faulty gates.