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Dive into the research topics where Naruhiko Nakanishi is active.

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Featured researches published by Naruhiko Nakanishi.


Applied Physics Letters | 2002

Hexagonal polymorph of tantalum–pentoxide with enhanced dielectric constant

Masahiko Hiratani; Shin Kimura; Tomoyuki Hamada; Shinpei Iijima; Naruhiko Nakanishi

A tantalum–pentoxide dielectric with an enhanced permittivity of over 50 was found to be crystallized in a hexagonal symmetry with a=0.628 nm and c=0.389 nm. The incommensurate epitaxy of tantalum pentoxide on hcp-ruthenium metal stabilizes the hexagonal phase with √3-time periodicity in plane, as compared with that of the known hexagonal δ phase. The crystallographic assumption, which is based on one-dimensional Ta–O–Ta chain along the c axis, can explain large polarizability caused by delocalized electrons on the one-dimensional chain.


Japanese Journal of Applied Physics | 2004

Novel Storage-Node Contacts with Stacked Point-Cusp Magnetron Sp-TiN Barrier for Metal–Insulator–Metal Ru/Ta2O5/Ru Capacitors in Gigabit Dynamic Random Access Memories

Tsuyoshi Kawagoe; Yoshitaka Nakamura; Keiji Kuroki; Isamu Asano; Hidekazu Goto; Naruhiko Nakanishi

We have investigated a mechanism for increasing the contact resistance (Rc) of the ruthenium (Ru) and the titanium nitride (TiN) barrier during the tantalum oxide (Ta2O5) oxidation annealing in the metal–insulator–metal (MIM) capacitors. It has been found that controlling the atomic ratio of Ti to N (Ti/N ratio) is a key to keeping the contact resistance low. Controlling the Ti/N ratio is easy for the sp-TiN, while it is difficult for the chemical-vapor-deposited TiN. On the basis of this result, we have proposed a novel Ru/TiN contact with a stacked-barrier structure fabricated by using the point-cusp magnetron (PCM) sputtering method. We have applied this structure to the MIM-Ru/Ta2O5/Ru capacitor in a gigabit DRAM with 0.10 µm design. In this capacitor, we have obtained the contact resistance of 10 kΩbit and the capacitor leakage current of 10-17 A/bit in the range of -1 to +1 V.


Archive | 2001

Semiconductor integrated circuit device and the method of producing the same

Shinpei Iijima; Yoshitaka Nakamura; Masahiko Hiratani; Yuichi Matsui; Naruhiko Nakanishi


Archive | 1999

Method of forming a semiconductor device including a capacitor with tantalum oxide (Ta2O5)

Yasuhiro Sugawara; Shinpei Iijima; Yuzuru Oji; Naruhiko Nakanishi; Misuzu Kanai; Masahiko Hiratani


Archive | 2003

Semiconductor device and process thereof

Yasuhiro Sugawara; Shinpei Iijima; Yuzuru Oji; Naruhiko Nakanishi; Misuzu Kanai


Archive | 2003

Method of forming a semiconductor device with a capacitor including a polycrystalline tantalum oxide film dielectric

Yasuhiro Sugawara; Shinpei Iijima; Yuzuru Oji; Naruhiko Nakanishi; Misuzu Kanai; Masahiko Hiratani


Archive | 1998

Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator

Naruhiko Nakanishi; Nobuyoshi Kobayashi; Yuzuru Ohji; Sinpei Iijima; Yasuhiro Sugawara; Misuzu Kanai


The Japan Society of Applied Physics | 1995

Precise Control of SiO2 Etching Characteristics Using Mono-Layer Adsorption of HF/H2O Vapor

Naruhiko Nakanishi; Nobuyoshi Kobayashi


The Japan Society of Applied Physics | 2003

Novel Storage-Node Contacts with Stacked PCM-Sp-TiN Barrier for MIM-Ru/Ta2O5/Ru Capacitors in Giga-Bit DRAMs

Tsuyoshi Kawagoe; Yoshitaka Nakamura; Keiji Kuroki; Isamu Asano; Hidekazu Goto; Naruhiko Nakanishi


應用物理 | 1997

Application of high-K dielectric material thin film to DRAM capacitors-Issues and a direction.

Yuzuru Ohji; Shinpei Iijima; Naruhiko Nakanishi; Isamu Asano

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