Naseef Mansoor

CDMA Enabled Wireless Network-on-Chip

Multihop communication links in conventional Networks-on-Chips (NoCs) results in lower rates of data transfer and higher energy dissipation. Long-range millimeter-wave wireless interconnects were envisioned to alleviate this problem. However, the available bandwidth of the wireless channels is limited and hence an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. In this article we show that with multiple simultaneous access of the shared wireless medium using a Code Division Multiple Access (CDMA) scheme the peak performance can be improved significantly while lowering energy dissipation in data transfer compared to the conventional wireline counterparts as well as state-of-the-art Wireless NoCs using similar technologies. We present a thorough analysis of the reliability in data transfer using the CDMA based wireless links and show that a reliability-aware architecture design with CDMA based wireless links can lower the energy dissipation in NoC fabrics without compromising the achievable robustness.

A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems

Computing modules in typical datacenter nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the destination chip over a wireline interconnect fabric. This multihop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to limitations of pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. Here, we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism

Wireless interconnects have emerged as an energy-efficient interconnection paradigm for multicore chips with Networks-on-Chips (NoCs). As wireless interconnects have the unique advantage of eliminating the need to layout physical channels they provide an inherent opportunity for dynamic reconfiguration of the NoC architecture. Large temporal and spatial variability in traffic patterns is expected in large multicore chips and especially in future heterogeneous systems-on-chips integrating different kinds of cores such as CPUs, GPUs, ASICs and memory. By establishing on-demand wireless links in response to dynamically varying traffic patterns the data bandwidth and energy efficiency of NoC architectures can be improved compared to static architectures with the same raw bandwidth. We present a dynamic medium access mechanism that establishes wireless links depending on traffic requirements while reducing the overheads. Such an interconnection system incorporating wireless links in a NoC fabric will be better suited to address non-uniformity and temporal variations in traffic patterns which are expected in future large multicore chips.

Design Methodology for a Robust and Energy-Efficient Millimeter-Wave Wireless Network-on-Chip

Wireless Network-on-Chip (WiNoC) architectures with CMOS compatible millimeter-wave (mm-wave) transceivers can achieve significant improvements in energy-efficiency in on-chip data transfer for multicore chips. A token based medium access mechanism is used in mm-wave WiNoC architectures to enable a distributed utilization of the available wireless bandwidth among multiple transmitters. However, on-chip wireless interconnects can suffer from high rates of failures due to challenges in design and manufacturing. Consequently, the token-passing mechanism can fail and significantly degrade the potential benefits of this novel interconnect technology. In this paper, we establish a cross-layer robust and failure-resistant design methodology for WiNoC architectures. By optimizing the WiNoC topology and complementing it with a robust token management scheme and error correction codes, we propose to design a failure-resistent WiNoC. Through system-level simulations, we demonstrate that the proposed design can mitigate the effect of various types of failures of the wireless fabric in WiNoC architectures without compromising the energy-efficiency.

Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas

On-chip wireless interconnects have emerged as a promising alternative to conventional wireline interconnects in Network-on-Chip (NoC) fabrics for multicore systems. However, it is not practical in the immediate future to arbitrarily scale up the number of wireless links without innovations in the physical layer. Here, we explore the design of a directional on-chip antenna based on a log-periodic structure. In this paper we propose the design of a wireless NoC (WiNoC) architecture with concurrent wireless links using these directional on-chip antennas. Through cycle accurate simulations we demonstrate that this novel WiNoC architecture attains better performance and energy efficiency compared to the state-of-the-art token based WiNoC of similar topology.

An energy-efficient and robust millimeter-wave Wireless Network-on-Chip architecture

Millimeter-wave (mm-wave) wireless interconnects have emerged as a promising solution to the energy-latency issues of global interconnects. Wireless Network-on-Chip (WiNoC) architectures with CMOS compatible mm-wave transceivers can achieve significant improvements in performance and energy-efficiency in on-chip data transfer for multicore chips. A token-based medium access mechanism is used in several mm-wave WiNoC architectures to enable a distributed and optimal utilization of the available wireless bandwidth among multiple transmitters. However, on-chip wireless interconnects being an emerging technology can suffer from high rates of failures. High frequency transceivers are especially vulnerable to noise. Consequently, failure of the token passing mechanism can significantly degrade the potential benefits of this novel interconnect technology. Traditional error correction mechanisms are not sufficient to recover from such errors as these can completely disable access to the wireless medium or result in excessive data corruption. On the other hand naturally occurring small-world networks are known to be highly efficient as well as inherently resilient to high rates of failures of nodes and links. Hence, in this paper, we propose the design of a small-world mm-wave WiNoC architecture augmented with a robust token management scheme to overcome the consequences of such failures while incurring marginal overheads.

Temperature-aware wireless network-on-chip architecture

Long-range wireless shortcuts in Network-on-Chip (NoC) architectures are shown to significantly improve energy-efficiency in on-chip data transfer. However, over-utilization of the wireless shortcuts and non-uniform traffic patterns may result in thermal hotpots in the NoC links or switches. In this work we propose a cross-layer approach of optimizing the NoC topology to achieve a balanced traffic distribution and temperature-aware routing (TAR) scheme to avoid thermal hotspots. We demonstrate that the proposed wireless NoC architecture is able to reduce temperature of NoC components and the TAR scheme is able to restrict the temperatures near a target threshold value.

A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architecture

Wireless Network-on-Chip (WiNoC) has emerged as a promising alternative to conventional wireline Network-on-Chip (NoC) architectures for integrating hundreds of cores on the same die due to higher data bandwidth and energy-efficiency. Token-based medium access mechanism is used in several WiNoC architectures to enable a distributed and optimal utilization of the available wireless bandwidth among multiple transmitters. Consequently, failure of the token passing mechanism can significantly degrade the potential benefits of this novel interconnect technology. In this paper, we propose the design of a small-world WiNoC architecture augmented with a robust token management scheme to overcome the consequences of such failures.

A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip

Long distance data communication over multi-hop wireline paths in conventional Networks-on-Chips (NoCs) cause high energy consumption and degradation in bandwidth. Wireless interconnects in the millimeter-wave band have emerged as an energy-efficient interconnection paradigm for multi-core chips interconnected with NoCs. However, spatial variations in traffic distribution and temporal variations in workloads can exert variable bandwidth demands on the NoC fabric. Wireless interconnects which do not require a physical layout of interconnects can be utilized to mitigate this issue. In order to dynamically allocate variable bandwidth to the wireless transceivers depending on the demand, the design of a dynamic and efficient Medium Access Control (MAC) mechanism to grant access to the on-chip wireless communication channel is needed. In this paper, a history based predictor, which can predict the bandwidth demand of the wireless nodes in the wireless NoC is designed. Based on these predicted demands we propose the design of two MAC mechanisms that are able to dynamically allocate bandwidth to the wireless transceivers. Through system level simulations, we show that the demand-aware MAC mechanisms are more energy efficient as well as capable of sustaining higher data bandwidth in wireless NoCs.

Intra-chip Wireless Interconnect: The Road Ahead

On-chip wireless interconnects have been proposed to provide energy-efficient data communication paths between cores in System-on-Chips (SoCs) in the multi and many-core era. Networks-on-Chips (NoCs) when interconnecting hundreds of cores consume large amounts of energy and suffer from high and unpredictable latency due to congestion at intermediate routers. Wireless interconnects alleviate this problem by providing direct single-hop links between distant cores in the chip. While various wireless NoC (WiNoC) architectures have been proposed and evaluated in the in the past decade this technology is not yet adopted in the mainstream industry. In order to benefit from the past decade of research in WiNoC designs a few important myths regarding wireless interconnects need to be dispelled while propelling the research to tangible technology transfer. In this paper several vectors that define the design space of WiNoCs will be identified while highlighting the state-of-the-art accomplishments in those directions by leading research groups. This will be followed by identifying the future direction that needs to be pursued to make WiNoCs a mainstream reality. At the end a few potential high-impact use-cases for wireless interconnects are discussed.