Shahriar Shamim

A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems

Computing modules in typical datacenter nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the destination chip over a wireline interconnect fabric. This multihop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to limitations of pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. Here, we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

Interference-Aware Wireless Network-on-Chip Architecture Using Directional Antennas

Wireless Network-on-Chip (WiNoC) has been recently introduced for addressing the scalability limitations of conventional multi-hop NoC architectures. Existing WiNoC architectures generally use millimeter-wave antennas without significant directional gains, along with token passing protocol to access the shared wireless medium. This limits the achievable performance benefits since only one wireless pair can communicate at a time. It is also not practical in the immediate future to arbitrarily scale up the number of non-overlapping channels by designing transceivers operating in disjoint frequency bands in the millimeter-wave spectrum commonly adopted for on-chip wireless interconnects. Consequently, we explore the use of directional antennas whereby multiple wireless interconnect pairs can communicate simultaneously. However, concurrent wireless communications can result in interference. This can be minimized in NoC by optimal placement of wireless interfaces (WIs) to maximize performance while minimizing interference. To address this, we propose an interference-aware WIs placement algorithm with routing strategy for WiNoC architecture by incorporating directional planar log-periodic antennas (PLPAs). This directional wireless network-on-chip (DWiNoC) architecture enables point-to-point links between transceivers and hence multiple wireless links can operate at the same time without interference.

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

With increase in complexity of multicore chips, efficiency of data transfer between cores of a chip is becoming increasingly challenging. Several novel on-chip network architectures are proposed to improve the design flexibility and communication efficiency in multicore chips. On the other hand, computing modules in typical data center nodes or server racks consist of several multicore chips on either a board or in a System-in-Package (SiP) environment. State-of-the-art interchip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the interchip channels to the destination chip. After reaching the destination chip they will be finally routed from the I/O to the internal nets there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Moreover, intrachip and interchip communication within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. In this work we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. This enables direct chip-to-chip communication between internal cores. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas

On-chip wireless interconnects have emerged as a promising alternative to conventional wireline interconnects in Network-on-Chip (NoC) fabrics for multicore systems. However, it is not practical in the immediate future to arbitrarily scale up the number of wireless links without innovations in the physical layer. Here, we explore the design of a directional on-chip antenna based on a log-periodic structure. In this paper we propose the design of a wireless NoC (WiNoC) architecture with concurrent wireless links using these directional on-chip antennas. Through cycle accurate simulations we demonstrate that this novel WiNoC architecture attains better performance and energy efficiency compared to the state-of-the-art token based WiNoC of similar topology.

Co-design of 3D wireless network-on-chip architectures with microchannel-based cooling

Three-dimensional Integrated Circuits (3D ICs) provide promising solutions to the challenges of footprint, device density and energy cost of on-chip communication. However, the increase in power density in 3D ICs due to reduced footprint aggravates the thermal issues in the chip. Liquid cooling through microfluidic channels can provide cooling capacities required for effective management of chip temperatures in 3D ICs. However, pumping liquid through the microchannels can cause high pressure drops causing structural instability in the chip. In order to reduce the pressure drops the height of the microchannels needs to be increased. This in turn makes the vertical interconnects realized by Through-Silicon-Vias longer, increasing delay and power consumption in data transfer. In this paper we propose to realize the vertical interconnects across the cooling layers with on-chip wireless interconnects. We present energy-efficient wireless 3D NoC architectures with optimal dimensions of microchannels for best thermal cooling capability and pressure characteristics.

Temperature-aware wireless network-on-chip architecture

Long-range wireless shortcuts in Network-on-Chip (NoC) architectures are shown to significantly improve energy-efficiency in on-chip data transfer. However, over-utilization of the wireless shortcuts and non-uniform traffic patterns may result in thermal hotpots in the NoC links or switches. In this work we propose a cross-layer approach of optimizing the NoC topology to achieve a balanced traffic distribution and temperature-aware routing (TAR) scheme to avoid thermal hotspots. We demonstrate that the proposed wireless NoC architecture is able to reduce temperature of NoC components and the TAR scheme is able to restrict the temperatures near a target threshold value.

A folded wireless network-on-chip using graphene based THz-band antennas

1 Long distance data communication over multi-hop wireline paths in conventional Network-on-Chips (NoCs) cause high-energy consumption and degradation in performance. Many emerging interconnect technologies such as 3D integration, photonic, Radio Frequency (RF), and wireless interconnects have been envisioned to alleviate the issues of a metal/dielectric interconnect system. To satisfy the increasing demand for high speed and low power interconnects, THz Wireless NoC (WiNoC) enabled with high-speed direct links between distant cores is desired. In this paper, we present an innovative approach to enable a THz WiNoC with low power wireless devices operating in the THz bands such as graphene based antennas. The novelty of this work is that we propose a torus like folding by using THz band links instead of global wires. With cycle accurate system-level simulations, we demonstrate that they are able to provide significant gains in performance and energy-efficiency in on-chip data transfer in NoC based multicore chips.

A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip

Long distance data communication over multi-hop wireline paths in conventional Networks-on-Chips (NoCs) cause high energy consumption and degradation in bandwidth. Wireless interconnects in the millimeter-wave band have emerged as an energy-efficient interconnection paradigm for multi-core chips interconnected with NoCs. However, spatial variations in traffic distribution and temporal variations in workloads can exert variable bandwidth demands on the NoC fabric. Wireless interconnects which do not require a physical layout of interconnects can be utilized to mitigate this issue. In order to dynamically allocate variable bandwidth to the wireless transceivers depending on the demand, the design of a dynamic and efficient Medium Access Control (MAC) mechanism to grant access to the on-chip wireless communication channel is needed. In this paper, a history based predictor, which can predict the bandwidth demand of the wireless nodes in the wireless NoC is designed. Based on these predicted demands we propose the design of two MAC mechanisms that are able to dynamically allocate bandwidth to the wireless transceivers. Through system level simulations, we show that the demand-aware MAC mechanisms are more energy efficient as well as capable of sustaining higher data bandwidth in wireless NoCs.

Intra-chip Wireless Interconnect: The Road Ahead

On-chip wireless interconnects have been proposed to provide energy-efficient data communication paths between cores in System-on-Chips (SoCs) in the multi and many-core era. Networks-on-Chips (NoCs) when interconnecting hundreds of cores consume large amounts of energy and suffer from high and unpredictable latency due to congestion at intermediate routers. Wireless interconnects alleviate this problem by providing direct single-hop links between distant cores in the chip. While various wireless NoC (WiNoC) architectures have been proposed and evaluated in the in the past decade this technology is not yet adopted in the mainstream industry. In order to benefit from the past decade of research in WiNoC designs a few important myths regarding wireless interconnects need to be dispelled while propelling the research to tangible technology transfer. In this paper several vectors that define the design space of WiNoCs will be identified while highlighting the state-of-the-art accomplishments in those directions by leading research groups. This will be followed by identifying the future direction that needs to be pursued to make WiNoCs a mainstream reality. At the end a few potential high-impact use-cases for wireless interconnects are discussed.