Nasir Ali Kant

Ultra-low-Voltage Integrable Electronic Realization of Integer- and Fractional-Order Liao’s Chaotic Delayed Neuron Model

The neurons are proven to show chaotic dynamical behavior, and due to this behavior, they find applications in several fields. Recently, the chaotic behavior of the neuron model using non-monotonous Liao’s activation function was described and its design using op-amp was presented. The presented design is a high-voltage one and is not integrable, as both passive resistors and inductors have been employed. Besides, most of the components are of floating type, which are difficult to design on an integrated chip. In addition, only integer-order design has been considered. In this paper, an ultra-low-voltage sinh-domain implementation of the neuron model has been introduced. Moreover, for the first time, the fractional-order implementation of the model has also been presented. The design offers the advantages of: (a) low-voltage implementation, (b) integrable design, (c) resistor and inductor less design, (d) using only grounded components, and (e) low-power design due to the inherent class AB nature of sinh-domain technique. The proper functioning of the model has been verified through different cases where the time constant of the integrator, delay and fractional order have been varied. The behavior of the neuron models is evaluated through HSPICE simulator using the metal oxide semiconductor transistor (MOSFET) models provided by Taiwan Semiconductor Manufacturing Company Limited (TSMC) 130 nm complementary metal oxide (CMOS) process.

Realization of Integrable Incommensurate-Fractional-Order-Rössler-System Design Using Operational Transconductance Amplifiers (OTAs) and Its Experimental Verification

In this paper, electronic implementation of fractional-order Rossler system using operational transconductance amplifiers (OTAs) is presented which until now was only being investigated through numerical simulations. The realization offers the benefits of low-voltage implementation, integrability and electronic tunability. In addition, the proposed circuit is a MOS only design (as no BJTs have been used) which contains only grounded components and is therefore suitable for monolithic VLSI design. The chaotic behavior of the fractional-order Rossler system in consideration with the incommensurate orders has been demonstrated which finds many applications in several fields. The theoretical predictions of the proposed implementation have been verified through experimentation and HSPICE simulator using Austrian Micro System (AMS) 0.35μm CMOS process and the obtained results have been found in good agreement with the Matlab simulink theoretical results obtained using FOMCON simulink toolbox. Besides, a secure message communication system has been considered to demonstrate fully the usefulness of the chaotic system.

Fractional-order filter design for ultra-low frequency applications

The paper presents a novel scheme to implement fractional-order filters for ultra-low frequency applications. The scheme is based on the intrinsic property of the fractional-order filters that the pole frequency can be scaled down to sub-hertz by employing the order if the normal pole frequency of the filter is designed slightly less than one. This is in contrast to the scaling techniques employed in low-frequency integer-order filters where the impedance is scaled to decrease the overall capacitance required for low-frequency design. The functioning of the scheme has been demonstrated by an OTA-based low-pass filter example implemented with 0.35μm technology node at ± 1.2V supply voltage.

Realization of Fractional-Order Double-Scroll Chaotic System Using Operational Transconductance Amplifier (OTA)

Realization of fractional-order double-scroll chaotic system using Operational Transconductance Amplifiers (OTAs) as active elements are presented in this paper. The fractional-order double-scroll chaotic system has been studied before as well using passive RC-ladder and tree-based structures but in this paper the requisite fractional-order integration has been accomplished through an integer-order multiple-feedback topology. As compared to double or multiple scroll chaotic systems existing in the open literature, the proposed realization offers the advantages of (a) low-voltage implementation, (b) integrablity as the design is resistor- and inductor-less and only grounded components have been employed in the design, and, (c) electronic tunability of the fractional order, time-constants and gain factors. In order to demonstrate the usefulness of the chaotic system, a simple secure message communication system has been designed and verified for its operation. The theoretical predictions of the proposed imp...

0.65V Integrable Electronic Realization of Integer- and Fractional-order Hindmarsh-Rose (HR) Neuron Model using Companding Technique

Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.

Log-domain realization of Fractional-Order Nonlinear Energy Operator (FNEO)

Implementation of the Fractional-Order Nonlinear Energy Operator employing the Log-Domain technique is demonstrated in this paper. The better performance of Fractional-Order Nonlinear Energy Operator compared to conventional Integer-Order Nonlinear Energy Operator in terms of extracting spikes from noise has been verified in the paper. As per the authors best knowledge, it is for the first time that the Fractional-Order Nonlinear Energy Operator is presented in the open literature. The Fractional-Order Nonlinear Energy Operator was designed at a supply voltage of 0.5V and the power consumption of the circuit was 109.3nW. The performance of the system has been evaluated using MOS transistor parameters provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 130-nm complementary MOS (CMOS) process.

Analog implementation of TDCNN single-cell architecture using sinh-domain companding technique

Temporal Derivative Cellular Neural Network (TDCNN) is an important class of neural networks. These networks find a lot of application in real life mostly in the real-time image processing. However, the main challenge is to implement this network in hardware. Therefore, in this paper, sinh-domain realization of single cell architecture of TDCNN which forms the only building block of complex TDCNN is introduced. The design offers the advantages of; a) low-power operation, b) electronic tunability, c) grounded components, and, d) Class AB nature. The functioning of the cell has been verified by simulation results achieved through HSPICE simulation tool employing CMOS 0.35 m process.

An ultra-low-voltage electronic implementation of inertial neuron model with nonmonotonous Liao’s activation function

Abstract The output of every neuron in neural network is specified by the employed activation function (AF) and therefore forms the heart of neural networks. As far as the design of artificial neural networks (ANNs) is concerned, hardware approach is preferred over software one because it promises the full utilization of the application potential of ANNs. Therefore, besides some arithmetic blocks, designing AF in hardware is the most important for designing ANN. While attempting to design the AF in hardware, the designs should be compatible with the modern Very Large Scale Integration (VLSI) design techniques. In this regard, the implemented designs should: only be in Metal Oxide Semiconductor (MOS) technology in order to be compatible with the digital designs, provide electronic tunability feature, and be able to operate at ultra-low voltage. Companding is one of the promising circuit design techniques for achieving these goals. In this paper, 0.5 V design of Liao’s AF using sinh-domain technique is introduced. Furthermore, the function is tested by implementing inertial neuron model. The performance of the AF and inertial neuron model have been evaluated through simulation results, using the PSPICE software with the MOS transistor models provided by the 0.18-μm Taiwan Semiconductor Manufacturer Complementary Metal Oxide Semiconductor (TSM CMOS) process.