Nathan Schneck
North Dakota State University
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Publication
Featured researches published by Nathan Schneck.
electro/information technology | 2014
Cherish Bauer-Reich; K. C. Tan; Fred Haring; Nathan Schneck; A. Wick; Layne A. Berge; Justin Hoey; Robert A. Sailer; Chad A. Ulven
A study was performed to assess the viability of using ultra-high frequency (UHF) radio frequency identification (RFID) to communicate with subsurface sensors. The results showed that, when the reader operated near the FCC limit, read ranges for the sensorwere greater than a half meter for soil moisture levels of 15% by weight or less. Moisture levels at 15% or greater resulted in significant attenuation or complete loss of signal. Tags also had desireable read ranges for depths up to 15 cm.
electronic components and technology conference | 2009
Nathan Schneck; Zane Johnson
An array of accelerated temperature cycling (ATC) finite element (FE) simulations using ANSYS™, and drop-impact finite element simulations using LS DYNA™, are used to find the optimum elastic modulus and coefficient of thermal expansion (CTE) for a stacked chip scale package. For the ATC simulations, Anands constitutive model with properties for Sn96.5Ag3.0Cu0.5 (SAC305) and tin-lead eutectic (Sn63Pb37) are used for the solder joint. The strain energy density is used as a damage parameter to determine the number of thermal cycles to failure. Tri-linear elastic-plastic models are used for the solder joint properties in the drop-impact simulations. The maximum normal stress in the solder joints is used as damage parameter for the drop-impact simulations. Simulations show that the optimum underfill material has an elastic modulus of 2 GPa and a CTE of 25 ppm/K.
intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2008
Nathan Schneck; Zane Johnson; Chris Schaff; Merideth Bell; James J. Stone
Drop testing is performed on stacked chip scale packages in eight configurations, including the use of two types of commercially available underfills. Full failure analysis using techniques such as dye penetrant and scanning electron microscopy (SEM) is performed. Corresponding explicit finite element simulations are performed using ANSYSreg LS-DYNA. These simulations are used to determine a suitable damage parameter and consequently, drop test life correlations are constructed. Considerable differences in drop impact reliability between Sn63Pb37 and SAC305 solder are observed.
Proceedings of SPIE | 2013
Val R. Marinov; Orven F. Swenson; Yuriy Atanasov; Nathan Schneck
Ultrathin flip-chip semiconductor die packaging on paper substrates is an enabling technology for a variety of extremely low-cost electronic devices with huge market potential such as RFID smart forms, smart labels, smart tickets, banknotes, security documents, etc. Highly flexible and imperceptible dice are possible only at a thickness of less than 50 μm, preferably down to 10-20 μm or less. Several cents per die cost is achievable only if the die size is ≤ 500 μm/side. Such ultrathin, ultra-small dice provide the flexibility and low cost required, but no conventional technology today can package such die onto a flexible substrate at low cost and high rate. The laser-enabled advanced packaging (LEAP) technology has been developed at the Center for Nanoscale Science and Engineering, North Dakota State University in Fargo, North Dakota, to accomplish this objective. Presented are results using LEAP to assemble dice with various thicknesses, including 350 μm/side dice as thin as 20 μm and less. To the best of our knowledge, this is the first report of using a laser to package conventional silicon dice with such small size and thickness. LEAP-packaged RFID-enabled paper for financial and security applications is also demonstrated. The cost of packaging using LEAP is lower compared to the conventional pick-and-place methods while the rate of packaging is much higher and independent of the die size.
intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2006
Zane Johnson; Nathan Schneck; Andrew R. Thoreson; James J. Stone
Moire interferometry and finite element (FE) analysis are used to quantify the deformation of stacked chip scale packages under thermal and accelerated thermal cycling loads. Basic thermo-elastic material property measurements are made of the constituent materials and found to be in good agreement with published values. Viscoplastic FE-based solder joint fatigue simulations indicate good reliability for several common design configurations of stacked packages
Microelectronic Engineering | 2013
Val R. Marinov; Orven F. Swenson; Yuriy Atanasov; Nathan Schneck
Archive | 2014
Cherish Bauer-Reich; Justin Hoey; Robert A. Sailer; Nathan Schneck; Chad A. Ulven
International Symposium on Microelectronics | 2010
Syed Sajid Ahmad; John Jacobson; Zane Johnson; Kevin Mattson; Aaron Reinholz; Nathan Schneck; Bernd Scholz; Greg Strommen
Archive | 2014
Cherish Bauer-Reich; Justin Hoey; Robert A. Sailer; Nathan Schneck; Chad A. Ulven
Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT) | 2014
Syed Sajid Ahmad; Fred Haring; Aaron Reinholz; Nathan Schneck