Nathaniel J. Quitoriano

Mechanical resonance of clamped silicon nanowires measured by optical interferometry

The mechanical resonance of laterally grown silicon nanowires measured by an optical interferometric technique is reported. The lengths and diameters of the nanowires ranged from L=2to20μm and D=39to400nm, respectively. The wires showed resonant frequencies in the f0=1–12MHz range and resonant quality factors Q at low pressure ranging from Q=5000 to Q=25000. The dependence of resonant frequency on the ratio of diameter to length squared, D∕L2, yielded a ratio of E∕ρ=9400±450m∕s. Assuming a density of ρ=2330kg∕m3, this experimental result yields an experimental Young modulus of E=205±10GPa, consistent with that of a bulk silicon. As the wires were cooled from T=270KtoT=77K, a 0.35% increase of resonant frequency was observed. This increase of resonant frequency with cooling resulted from a change in Young’s modulus and from the thermal contraction of silicon. The quality factor did not vary significantly from P=10−4to102Torr, suggesting that viscous damping does not dominate the dissipative processes in th...

Integratable Nanowire Transistors

We report a structure to control nanowire location and growth direction and demonstrate top-gated, metal-oxide-semiconductor, field-effect transistors (MOSFETs) using this structure. The nanowires wereengineered to grow against an oxide surface of a (001), silicon-on-insulator substrate, enabling straightforward fabrication of MOSFETs exhibiting an Io/Ioff ratio approximately 104 and a subthreshold slope of approximately 155 mV/decade. Though nanowires were engineered to grow in (110) directions, the nanowires still grew by the addition of {111) planes.

Single-crystal, Si nanotubes, and their mechanical resonant properties.

Single-crystalline Si nanotubes (NTs) were fabricated using vapor-liquid-solid grown, Ge nanowires (NWs) as a template upon which a Si shell was deposited to first grow Ge-core, Si-shell NWs. The tips of these NWs were removed, enabling exposure of the Ge core to H(2)SO(4) and H(2)O(2). After removing the Ge core, single-crystalline Si NTs remained. In addition to growing these Ge-core, Si-shell NWs from a Si (111) substrate, these NWs were also grown horizontally from a vertical Si surface to enable the fabrication of horizontal NTs after focused ion-beam cutting and etching steps. The resonant properties of the Ge-core, Si-shell NW, and the Si NT after the cutting and etching steps were measured and found to have a quality factor, Q, of approximately 1800.

Guiding vapor?liquid?solid nanowire growth using SiO2

Vapor-liquid-solid (VLS) grown nanowires (NWs) typically grow in [Formula: see text] directions. In this work, using guiding structures, we effectively grow Si NWs with diameters between 20 and 100 nm in both [001] and <110> directions by guiding the Si NW growth using SiO(2) surfaces. Using one structure, we demonstrate NW growth in the substrate plane, against the buried oxide layer of a standard, (001) silicon-on-insulator wafer. Using the other structure, we demonstrate NW growth perpendicular to a (001) substrate. We show that the VLS growth mechanism is the same as unconstrained NW growth, with the NWs still growing by the addition of {111} planes. We show that when the guiding surface is removed, the NW grows in its natural growth direction because the growth mechanism has not changed. We speculate that NW growth can be guided with a range of materials, the most suitable being those that are amorphous and those which are nearly immiscible both with the catalyst and with the NW material.

Using pn junction depletion regions to position epitaxial nanowires

Si nanowires were grown horizontally using the vapor-liquid-solid method from vertical {111} surfaces etched into a (110) Si substrate. The nanowires were catalyzed by negatively charged, citrate-stabilized, Au nanoparticles. The negative charge on the nanoparticles was used to position them along a positively charged depletion region formed by a pn junction. By positioning the nanoparticle catalysts, the epitaxial Si nanowires catalyzed by the nanoparticles were also positioned along this junction. The structure that best positioned the nanowires was highly doped n-type material on a lightly doped p-type substrate. Enhanced positioning of the nanowires was accomplished using a reverse bias across the pn junction.

Characterizing defects and transport in Si nanowire devices using Kelvin probe force microscopy.

Si nanowires (NWs) integrated in a field effect transistor device structure are characterized using scanning electron (SEM), atomic force, and scanning Kelvin probe force (KPFM) microscopy. Reactive ion etching (RIE) and vapor-liquid-solid (VLS) growth were used to fabricate NWs between predefined electrodes. Characterization of Si NWs identified defects and/or impurities that affect the surface electronic structure. RIE NWs have defects that both SEM and KPFM analysis associate with a surface contaminant as well as defects that have a voltage dependent response indicating impurity states in the energy bandgap. In the case of VLS NWs, even after aqua regia, Au impurity levels are found to induce impurity states in the bandgap. KPFM data, when normalized to the oxide-capacitance response, also identify a subset of VLS NWs with poor electrical contact due to nanogaps and short circuits when NWs cross that is not observed in AFM images or in current-voltage measurements when NWs are connected in parallel across electrodes. The experiments and analysis presented outline a systematic method for characterizing a broad array of nanoscale systems under device operation conditions.

Lateral, Ge, nanowire growth on SiO2

Vapor-liquid-solid (VLS) nanowires (NWs) typically grow in [111] directions. Previously, the authors have demonstrated guided Si NW growth, engineering the VLS NWs to grow in a [110] direction against a SiO(2) surface. In this work, the authors demonstrate guided high-quality Ge nanowire growth against a SiO(2) surface in the substrate plane to bridge between two Si mesas. The authors explore the interfaces between a Ge NW and the two Si device-layer mesas and report high-quality, epitaxial interfaces between the Ge NW and both Si mesas.

Lateral, high-quality, metal-catalyzed semiconductor growth on amorphous and lattice-mismatched substrates for photovoltaics

Solar-derived energy is universally available but is not yet cost-competitive. Next generation solar cells are expected to have high efficiencies, associated with single-crystalline semiconductors, at reduced costs, associated with amorphous substrates. Here we report the growth of high-quality semiconductors (Ge and Si) on amorphous and lattice-mismatched substrates using metal-catalyzed, lateral growth. Using this technique, we engineer the location of crystal nucleation, by controlling the catalyst location, and can thus prevent the formation of grain boundaries, typical when crystals grow together. The results presented here provide a foundation upon which next generation photovoltaics may be built.

Ideal, constant-loss nanophotonic mode converter using a Lagrangian approach.

Coupling light between an optical fiber and a silicon nanophotonic waveguide is a challenge facing the field of silicon photonics to which various mode converters have been proposed. Inverted tapers stand out as a practical solution enabling efficient and broadband mode conversion. Current design approaches often use linearly-shaped tapers and two dimensional approximations; however, these approaches have not been rigorously verified and there is not an overarching design framework to guide the design process. Here, using a Lagrangian formulation, we propose an original, constant-loss framework for designing shape-controlled photonic devices and apply this formalism to derive an ideal constant-loss taper (CLT). We specifically report on the experimental demonstration of a fabrication-tolerant, 15-µm-long CLT coupler, that produces 0.56 dB fiber-chip coupling efficiency, the highest efficiency-per-length ratio ever reported.

Photoluminescence from low thermal budget silicon nano-crystals in silica.

We have developed a novel method to fabricate Si nanocrystals in a silica matrix with a considerably reduced thermal budget using pulsed laser deposition. Normally, Si nanocrystals are formed through phase separation by annealing a Si-rich SiO2 film at 1100 °C; we show Si nanocrystal formation in as-deposited films at 550 °C. We suggest the mechanism for this is through surface diffusion during deposition. We also show the ability to vary the size of these nanocrystals by adjusting the deposition conditions and can increase their size through annealing. If the nanocrystals are small they have excellent photoluminescence properties however larger nanocrystals have poor luminescence.