Nau Ozaki

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications

A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.

Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC

Image recognition algorithm is becoming one of the most important technology for intelligent vehicle application such as Advanced Driver Assistance Systems (ADAS), however its computational costs are still considerably high. To realize such applications using image recognition algorithm as hard real-time task with low power consumption, we have developed heterogeneous multi-core SoC specialized for image recognition [1]. Subsequently, several image recognition applications have been developed using this SoC. In this paper, we address two ADAS applications and image recognition algorithms for them, and evaluate them on the SoC. The results of the evaluation show that the SoC allows these applications to run with significantly low power consumption comparing with general purpose CPU.

A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication

A 1.4Mpixel CMOS image sensor (CIS) with multiple row-rescan (MRR) based data sampling for optical camera communication (OCC) is presented. The CIS achieves a data sampling rate at a row-scan rate of 51kS/s even with a frame rate of 30fps, a pixel size of 2.2mm × 2.2mm by multiply rescanning the rows at a modulated LED spot. The detectable minimum LED size projected onto the CIS becomes 13.2mm × 13.2mm. The MRR could be a practical solution for IEEE 802.15.SG7a OCC.