Hideaki Majima

A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations

An automatic amplitude control circuit to minimize the phase noise of a LC-VCO is proposed and implemented by a 0.18-/spl mu/m CMOS process. The phase noise lower than -90dBc/Hz at 100kHz offset is achieved over a wide tuning range (from 2.2GHz to 2.8GHz) under large process (/spl Delta/V/sub th/ = /spl plusmn/100mV), temperature (from /spl sim/35/spl deg/C to 85/spl deg/C), and power supply (from 1.8V to 3V) variations.

A 1.2-V CMOS complex bandpass filter with a tunable center frequency

A 4th-order complex bandpass filter (BPF) with a tunable center frequency is designed and fabricated in a 0.13 /spl mu/m CMOS technology. The transfer function is changeable dynamically. The passband center frequency can be set to 0 Hz, 1 MHz, 1.5 MHz and 2 MHz so that the filter can work as a complex BPF in the receiver path and as a LPF in the transmit path. An opamp-RC filter is used to obtain a wide dynamic range. The filter operates with the supply voltage as low as 1.2 V. The input referred noise for 1.4 MHz band width is 53 /spl mu/Vrms. IIP3 and the image rejection ratio at 1.5 MHz is 25.2 dBm and 52 dB, respectively.

A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter

The frequency drift of an open-loop PLL is an issue for direct modulation applications such as Bluetooth transceivers. The drift mainly comes from the temperature variation of the VCO during the TX operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through full-chip thermal analysis. Moreover, a novel temperature-compensated VCO by employing a new biasing scheme is proposed. The combination of these two techniques enables power reduction of the transmitter by 33% without sacrificing performance.

A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch trimming circuit

A single-chip low-IF transmitter for the Bluetooth enhanced data rate (max. 3Mbps) was fabricated in 0.18-/spl mu/m CMOS process. A quantitative study on the relation between the VCO pulling, intermediate frequency, and the linearity of the PA shows that the 1MHz-IF is the best solution. By a digital DC offset cancellation and I/Q mismatch trimming techniques, the LO and image signal leakages are suppressed below -40dBc and -50dBc, respectively.

A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control

A low-voltage, low-power class-D VCO is presented. An LDO based dynamic supply voltage control technique for the class-D VCO is proposed, which realizes fast and reliable start-up and extremely low-voltage operation of the class-D VCO. The proposed LDO-VCO is fabricated using a 28 nm CMOS technology. The measured phase noise is -115.9 dBc/Hz at 1 MHz offset from the 2.35 GHz carrier, while drawing the current of 760 μA from 0.5 V LDO input. The class-D VCO core consumes 0.171 mW from 225 mV LDO output and the FoM is 191.0 dBc/Hz.

A 65nm CMOS, 1.5-mm Bluetooth transceiver with integrated antenna filter for Co-existence with a WCDMA transmitter

This paper presents a fully integrated Bluetooth transceiver in a 65 nm CMOS, which occupies 1.5 mm2 on the chip. It even integrates an antenna filter to reject blocker from the co-existing wireless system such as WCDMA and GSM. The frequency response of the antenna filter is controlled by an onchip temperature monitor. The antenna filter achieves 30 dB rejection over the entire WCDMA band-I of 1920-1980 MHz with the temperature range from -40 to 80 °C. The transceiver achieves RX sensitivity of -89.1 dBm and TX output level of +4 dBm.

Low frequency spurs of VCO due to noise propagation from digital I/O's and their effects on performance of Bluetooth SoC

This paper describes the effect of digital noise on RF circuits on the single chip Bluetooth SoC. Low frequency components in the digital noise, generated by I/O circuits accessing to an external memory, are found to be converted to the phase noise as the spurs of voltage controlled oscillator (VCO). The spurs bring the performance degradation of wireless communications systems. To manage the gain of the VCO and the coupling coefficient is shown to be a key to mitigate the performance degradations.

A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication

A 1.4Mpixel CMOS image sensor (CIS) with multiple row-rescan (MRR) based data sampling for optical camera communication (OCC) is presented. The CIS achieves a data sampling rate at a row-scan rate of 51kS/s even with a frame rate of 30fps, a pixel size of 2.2mm × 2.2mm by multiply rescanning the rows at a modulated LED spot. The detectable minimum LED size projected onto the CIS becomes 13.2mm × 13.2mm. The MRR could be a practical solution for IEEE 802.15.SG7a OCC.

A 90nm CMOS highly linear clock bootstrapped RF sampler operating at wide frequency range of 0.5GHz to 5GHz

This paper reports a highly linear RF sampler with wide operating frequency range and power supply range. A clock bootstrapping circuit is proposed to decrease both the on-resistance and off-leakage of advanced MOSFETs while considering the device reliability. The proposed RF sampler circuit has been implemented in 90nm CMOS process, and excellent IIP3 has been obtained at wide frequency range up to 5GHz and 2GHz when the power supply is 1.2V and 0.5V, respectively.

A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN

This paper presents a low voltage 5GHz WLAN receiver (RX) with 0.8V power supply. The RX targets 802.11ax standard implemented in CMOS technology node from 28nm to 14nm whose power supply voltage will decrease to 0.8V. The RX presents three key techniques that overcome the challenges for the low voltage operation. An RF amplifier employs a variable source degeneration to improve the linearity. A quadrature demodulator adopts a low noise biasing technique to obtain sufficiently high overdrive voltage in a passive mixer. A 3-stage feedforward operational amplifier increases the gain within 40MHz bandwidth. The RX was fabricated in 28nm CMOS process. The measurement results show the gain from −2 to 54dB, 4.3dB of NF, and −36.1dB of EVM with VHT80 256QAM when the power supply voltage is 0.8V. The presented RX achieves low voltage operation while maintaining sufficient WLAN performances.