Naveed Imran

Event recognition from photo collections via PageRank

We propose a method of mining most informative features for the event recognition from photo collections. Our goal is to classify different event categories based on the visual content of a group of photos that constitute the event. Such photo groups are typical in a personal photo collection of different events. Visual features are extracted from the images, yet the features from individual images are often noisy and not all of them represent the distinguishing characteristics of an event. We employ the PageRank technique to mine the most informative features from the images that belong to the same event. Subsequently, we classify different event categories using the multiple images of the same event because we argue that they are more informative about the content of an event rather than any single image. We compare our proposed approach with the standard bag of features method (BOF) and observe considerable improvements in recognition accuracy.

Fault Demotion Using Reconfigurable Slack (FaDReS)

We propose an active dynamic redundancy-based fault-handling approach exploiting the partial dynamic reconfiguration capability of static random-access memory-based field-programmable gate arrays. Fault detection is accomplished in a uniplex hardware arrangement while an autonomous fault isolation scheme is employed, which neither requires test vectors nor suspends the computational throughput. The deterministic flow of the fault-handling scheme achieves an improved recovery in a bounded number of reconfigurations. This approach extends existing signal processing properties to accommodate fault handling, and is validated by implementing an H.263 video encoder discrete cosine transform (DCT) block. The peak signal-to-noise ratio measure of the video sequences indicates fault tolerance in the DCT block with only limited quality degradation, during the isolation and recovery phases spanning a few frames.

Self-Adapting Resource Escalation for Resilient Signal Processing Architectures

To deal with susceptibility to aging and process variation in the deep submicron era, signal processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. The Priority Using Resource Escalation (PURE) online resiliency approach is developed herein to maintain throughput quality based on the output Peak Signal-to-Noise Ratio (PSNR) or other health metric. PURE is evaluated using an H.263 video encoder and shown to maintain signal processing throughput despite hardware faults. Its performance is compared to two alternative reconfiguration algorithms which prioritize the optimization of the number of reconfiguration occurrences and the fault detection latency, respectively. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. Compared to the alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. The results indicate the benefits of priority-aware resiliency over conventional redundancy in terms of fault-recovery, power consumption, and resource-area requirements.

A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution

We employ output-discrepancy consensus to mitigate faulty modules of a Triple Modular Redundant (TMR) arrangement using dynamic partial reconfiguration. Traditionally, the fault-handling resilience of a TMR arrangement is limited to fault(s) in a single TMR instance over the entire mission duration. An additional permanent fault in any of two other TMR instances results in missions failure. However, in this work, a novel Self-Configuring approach for Discrepancy Resolution (SCDR) is developed and assessed. In SCDR, the occurrence of faults in more than one module initiates the repair mechanism, then upon fault recovery, the system is configured into Concurrent Error Detection (CED) mode. The approach is validated by the complete recovery of a TMR realization of 25 stage Finite Impulse Response (FIR) filter implemented on a reconfigurable platform as a case study. The results show that a self-healing circuit can be realized exploiting the dynamic partial reconfiguration capability of FPGAs while requiring a streamlined operational data path compared to TMR.

Electronic media, creativity and plagiarism

This article provides an introduction to plagiarism and the numerous negative aspects associated with it. Some examples from history have also been provided along with their outcomes. There are different types of plagiarism with varying legal and social aspects. The taxonomy of plagiarism is built by classifying it, with respect to the method involved in plagiarism, the form in which it happens or the intention of the plagiarist. The strategies suggested in the literature to avoid plagiarism are organized into individual and organizational levels. Individuals can adopt strategies to build habits of avoiding plagiarism and focus on their original and innovative way of thinking. Similarly, institutions can make policies to cope with plagiarism and hence maintain their reputation. In this paper, the focus is not on mentioning the plagiarism detection methods; rather we believe that building awareness in the people about plagiarism outcomes is more important than teaching them about the different methodologies used for detection. Some students avoid plagiarism detection as if playing a game and it can be only avoided by educating them in ethics.

Activity-Based Resource Allocation for Motion Estimation Engines

An architecture proof-of-concept which adapts the throughput datapath based on the anticipation of computational demand in dynamic environments is demonstrated and evaluated for a motion estimation (ME) engine. The input signal characteristics are exploited to anticipate the time varying computational complexity as well as to instantiate dynamic replicas (DRs) to realize fault-resilience. The scheme employs amorphous processing elements (APEs) which either perform as active elements (AEs) to maintain quality/throughput, serve as DRs to increase reliability levels, or hibernate passively as reconfigurable slack (RS) available to other tasks. Experimental results from a hardware platform for field programmable gate array (FPGA)-based video encoding demonstrate power efficiency and fault-tolerance of the ME engine. A significant reduction in power consumption is achieved ranging from 83% for low-motion-activity scenes to 12.5% for high motion activity video scenes. The scenes motion activity is utilized to improve redundancy for the purpose of priority based diagnosis of the computing modules. In addition, a graceful degradation strategy is developed to recover from hard errors by adapting the search range of candidate motion vectors (MVs). This adaptive hardware scheme is shown to automatically demote the faulty resources in FPGA devices based on streaming performance.

Power and quality-aware image processing soft-resilience using online multi-objective GAs

A self-aware signal processing architecture is proposed based on adaptive resource escalation which is guided by a multi-objective genetic algorithm (GA). The GA prioritises tasks within a reconfigurable hardware fabric to maintain the quality-of-service and power consumption objectives. Attainment of these objectives is subject to the intrinsic reliability and performance of the computational elements in the resource pool. A health metric at the application layer, such as peak-signal-to-noise ratio (PSNR) measurement in a discrete cosine transform (DCT) or measure of confidence in a support vector machine (SVM) classifier, is used to assess throughput performance. When performance decreases beyond acceptable tolerances, the primary objective is to maximally recover output quality. The secondary objective is to minimise power consumption which also depends upon the input signal characteristics, in addition to the utilised computational resources. An adaptive guidance function for GA-driven recovery is proposed and validated for these objectives. It retains healthy processing elements in the throughput data path to gracefully-degrade throughput by optimising resource selection.

Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input

Distance-Ranked Fault Identification (DRFI) is a dynamic reconfiguration technique which employs runtime inputs to conduct online functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set of functionally identical bitstream configurations are created which utilize alternate hardware resources in the FPGA fabric. An ordering is imposed on the configuration pool as updated by the PageRank indexing precedence. The configurations which utilize permanently damaged resources and hence manifest discrepant outputs, receive lower rank are thus less preferred for instantiation on the FPGA. Results indicate accurate identification of fault-free configurations in a pool of pregenerated bitstreams with a low number of reconfigurations and input evaluations. For MCNC benchmark circuits, the observed reduction in input evaluations is up to 75% when comparing the DRFI technique to unguided evaluation. The DRFI diagnosis method is seen to isolate all 14 healthy configurations from a pool of 100 pregenerated configurations, and thereby offering a 100% isolation accuracy provided the fault-free configurations exist in the design pool. When a complete recovery is not feasible, graceful degradation may be realized which is demonstrated by the PSNR improvement of images processed in a video encoder case study.

Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation

A conventional Concurrent Error Detection (CED) technique usually relies on two exact replicas of a given module to provide redundancy in fault-tolerant systems. A discrepancy in one of the two instances flags at least one of them as faulty. We propose a heterogenous redundant FPGA-based system by exploiting the application properties. Consequently, the replicated module is not necessarily an exact copy of the original module but is much less resource and power hungry. In the paper, we discuss two forms of the heterogeneous structure which are spatial and temporal redundancy based. These forms are evaluated using FPGA based hardware implementation of the Discrete Cosine Transform (DCT) block. A necessary condition is derived to declare the DCT block as fault-free. The results show that the heterogeneous spatial redundancy can realize a resource efficient CED pair at the cost of a small latency in error detection. On the other hand, the heterogeneous temporal redundancy can provide permanent faults resource coverage at the cost of reduced throughput with negligible resource overhead.

Emerging resilience techniques for embedded devices

This chapter presents a broad range of techniques for highly reliable and survivable field programmable gate array-based embedded computing systems operating in harsh environments. The notion of autonomous self-repair is essential for such systems as physical access to such platforms is often limited. In this regard, adaptable reconfiguration-based techniques are presented in this chapter, whereby an appropriate set of resources can be selected at runtime to achieve graceful performance degradation in the presence of multiple permanent and transient faults. Intermittent quality of repair (QoR) can be achieved by use of proposed genetic algorithm-based intelligent techniques for relatively compact circuits as compared to conventional approaches. Video encoder use cases are used as benchmarks, and significance driven resource allocation is utilized to demonstrate benefit in terms of recovery time, throughput degradation, and QoR. These metrics can be utilized as a gauge for evaluating the efficacy of multiple FH techniques. Finally, a discussion of real-time tradeoffs of resilience, quality, and energy for proposed approaches is presented.