Rizwan A. Ashraf

Understanding the propagation of transient errors in HPC applications

Resiliency of exascale systems has quickly become an important concern for the scientific community. Despite its importance, still much remains to be determined regarding how faults disseminate or at what rate do they impact HPC applications. The understanding of where and how fast faults propagate could lead to more efficient implementation of application-driven error detection and recovery. In this work, we propose a fault propagation framework to analyze how faults propagate in MPI applications and to understand their vulnerability to faults. We employ a combination of compiler-level code transformation and instrumentation, along with a runtime checker. Using the information provided by our framework, we employ machine learning technique to derive application fault propagation models that can be used to estimate the number of corrupted memory locations at runtime.

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

In this work, Field-Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist-Driven Evolutionary Refurbishment technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1 percent in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware-Based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations. Successful refurbishment of the apex4 circuit having a total of 1,252 LUTs with 10 percent spares is achieved in as few as 633 generations on average when subjected to simulated randomly injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs

This paper investigates the ability to provide improved Reliability of TMR systems at comparable area and time cost using design diversity. Namely, we evaluate multiple implementations of the same functional design using a repository of methods: Templates, Case-Based, Inverted-Output, and NAND/NOR-Based methods. The design methods are tested on multiple benchmark circuits in different TMR setups for each of which design diversity and fault tolerance are examined. The results show that extensive design diversity can be achieved at design-time using one or a combination of these methods, and verifies the increased fault-tolerance of TMR-based systems with diverse designs in multiple failure modes at run-time. Moreover, results indicate that improved system fault-tolerance can be achieved using designs from different classes of design techniques, rather than using variations of the same design method without incurring a run-time expense.

Applicability of power-gating strategies for aging mitigation of CMOS logic paths

Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, Power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping. Results indicate the effectiveness of power-gating on NBTI/PBTI phenomena and propose a preferred sleep transistor configuration for maximizing higher recovery.

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains

Although the trend of technology scaling is sought to realize higher performance computer systems, it also results in Integrated Circuits (ICs) suffering from increasing Process, Voltage, and Temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guardband is not reserved. In this work, we propose the Reactive Rejuvenation (RR) architectural approach consisting of detection and recovery phases to mitigate circuit from BTI-induced aging. The BTI impact on the critical and near critical paths performance is continuously examined through a lightweight logic circuit which asserts an error signal in the case of any timing violation in those paths. By utilizing timing violation occurrence in the system, the timing-sensitive portion of the circuit is recovered from BTI through switching computations to redundant aging-critical voltage domain. The proposed technique achieves aging mitigation and reduced energy consumption as compared to a baseline circuit. Thus, significant voltage guardbands to meet the desired timing specification are avoided.

Designing energy-efficient approximate adders using parallel genetic algorithms

Approximate computing involves selectively reducing the number of transistors in a circuit to improve energy savings. Energy savings may be achieved at the cost of reduced accuracy for signal processing applications whereby constituent adder and multiplier circuits need not generate a precise output. Since the performance versus energy savings landscape is complex, we investigate the acceleration of the design of approximate adders using parallelized Genetic Algorithms (GAs). The fitness evaluation of each approximate adder is explored by the GA in a non-sequential fashion to automatically generate novel approximate designs within specified performance thresholds. This paper advances methods of parallelizing GAs and implements a new parallel GA approach for approximate multi-bit adder design. A speedup of approximately 1.6-fold is achieved using a quad-core Intel processor and results indicate that the proposed GA is able to find adders which consume 63:8% less energy than accurate adders.

Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region

A near-threshold voltage (NTV) operation provides a recognized approach to low-power circuit design due to its balancing of minor performance degradation relative to its significant power savings. However, the scaling voltage and the technology process give rise to increased susceptibility to radiation-induced soft errors for systems operating at NTV. In this brief, we develop new results for the evaluation of alternatives to mask single-event transients in combinational logic and single-event upsets in storage elements for three commonly utilized redundancy approaches, namely, spatial, temporal, and a hybrid of both spatial and temporal. The performance and energy impact of each approach is quantified at the NTV operation. Additionally, the impact of an increased effect of threshold voltage variation at NTV is assessed for all redundant systems. We also investigate the effect of technology scaling by comparing the energy and performance variation of the 45-nm MOSFET planar and the 16-nm high-

Activity-Based Resource Allocation for Motion Estimation Engines

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Power and quality-aware image processing soft-resilience using online multi-objective GAs

metal-gate bulk fin-typed field-effect transistor structures as modeled by the Predictive Technology Model NanGate open source library via simulations in HSPICE. The results indicate that delay variation of temporal redundancy (22.34%) is lower than the variation of both triple module redundancy and self-voting dual module redundancy (31.6% and 35.2%, respectively), although the variation of 16-nm is beneath that of 45-nm technology node for both. On average, operating at NTV using trigate 16-nm bulk FinFET devices reduces energy consumption and incurs less performance impact for redundant systems. Utilizing temporal redundancy based on a trigate 16-nm process achieves 56.2% energy savings at a 27.6% delay increase compared with a spatial redundancy approach.

Sustainability assurance modeling for SRAM-based FPGA evolutionary self-repair

An architecture proof-of-concept which adapts the throughput datapath based on the anticipation of computational demand in dynamic environments is demonstrated and evaluated for a motion estimation (ME) engine. The input signal characteristics are exploited to anticipate the time varying computational complexity as well as to instantiate dynamic replicas (DRs) to realize fault-resilience. The scheme employs amorphous processing elements (APEs) which either perform as active elements (AEs) to maintain quality/throughput, serve as DRs to increase reliability levels, or hibernate passively as reconfigurable slack (RS) available to other tasks. Experimental results from a hardware platform for field programmable gate array (FPGA)-based video encoding demonstrate power efficiency and fault-tolerance of the ME engine. A significant reduction in power consumption is achieved ranging from 83% for low-motion-activity scenes to 12.5% for high motion activity video scenes. The scenes motion activity is utilized to improve redundancy for the purpose of priority based diagnosis of the computing modules. In addition, a graceful degradation strategy is developed to recover from hard errors by adapting the search range of candidate motion vectors (MVs). This adaptive hardware scheme is shown to automatically demote the faulty resources in FPGA devices based on streaming performance.