Navin Srivastava

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.

Performance analysis of carbon nanotube interconnects for VLSI applications

The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Using this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. The technological requirements necessary to make CNT bundles viable as future interconnects are also laid out.

A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy

Three-dimensional (3D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3D technology under the influence of such thermal constraints. Using a processor-cache-memory system and carefully chosen applications encompassing different memory behaviors, the performance of 3D architecture is compared with a conventional planar (2D) design. It is found that the substantial increase in memory bus frequency and bus width contribute to a significant reduction in execution time with a 3D design. It is also found that increasing the clock frequency translates into larger gains in system performance with 3D designs than for planar 2D designs in memory intensive applications. The thermal profile of the vertically stacked chip is generated taking into account the highly temperature sensitive leakage power dissipation. The maximum allowed operating frequency imposed by temperature constraint is shown to be lower for 3D than for 2D designs. In spite of these constraints, it is shown that the 3D system registers large performance improvement for memory intensive applications

Are carbon nanotubes the future of VLSI interconnections

Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper and thereby extend the lifetime of electrical interconnects. This paper examines the state-of-the-art in CNT interconnect research and discusses both the advantages and challenges of this emerging nanotechnology

Carbon nanotube interconnects: implications for performance, power dissipation and thermal management

This paper presents a comprehensive evaluation of carbon nanotube bundle interconnects from all aspects critical to VLSI circuits - performance, power dissipation and reliability - while taking into account practical limitations of the technology. A novel delay model for CNT bundle interconnects has been developed, using which it is shown that CNT bundles can significantly improve the performance of long global interconnects with minimal additional power dissipation (for maximum metallic CNT density). While it is well known that CNT bundle interconnects can carry much higher current densities than copper, their impact on back-end thermal management and interconnect temperature rise is presented here for the first time. It is shown that the use of CNT bundle vias integrated with copper interconnects can improve copper interconnect lifetime by two orders of magnitude and also reduce optimal global interconnect delay by as much as 30%

Current Status and Future Perspectives of Carbon Nanotube Interconnects

In this paper, we review the current status of CNT interconnect research, from both fabrication and modeling aspects. The fabrication issues of vertical and horizontal CNT interconnects and remaining challenges are discussed. State-of-the-art in both SWCNT and MWCNT modeling and performance analysis are presented. In addition, high-frequency effects, off-chip application, and process variation of CNT interconnects have also been discussed.

Exponential Data Fitting and its Applications

Type Ia supernova light curves are characterized by a rapid rise from zero luminosity to a peak value, followed by a slower quasi-exponential decline. The rise and peak last for a few days, while the decline persists for many months. It is widely believed that the decline is powered by the radioactive decay chain 56Ni → 56Co → 56Fe, but the rates of decline in luminosity do not exactly match the decay rates of Ni and Co. In 1976, Rust, Leventhal, and McCall [19] presented evidence that the declining part of the light curve is well modelled by a linear combination of two exponentials whose decay rates were proportional to, but not exactly equal to, the decay rates for Ni and Co. The proposed reason for the lack of agreement between the rates was that the radioactive decays take place in the interior of a white dwarf star, at densities much higher than any encountered in a terrestrial environment, and that these higher densities accelerate the two decays by the same factor. This paper revisits this model, demonstrating that a variant of it provides excellent fits to observed luminosity data from 6 supernovae.

Carbon Nanotube Vias: Does Ballistic Electron–Phonon Transport Imply Improved Performance and Reliability?

This paper investigates the electron and phonon transport and their implications for performance and reliability of single-walled carbon nanotube (SWCNT), double-walled carbon nanotube (DWCNT), and multiwalled carbon nanotube (MWCNT) vias-possibly the most imminent application of carbon nanotube (CNT)-based components in very large scale integration chips. Accurate resistance and thermal conductance models are provided for isolated CNTs, as well as bundles of these, based on detailed electrical and thermal transport physics in the submicrometer regime. It is found that although CNT vias are both electrically and thermally in the ballistic regime, their electrical and thermal performance still cannot match that of Cu via. While the large resistance of CNT vias may not be a significant concern for local interconnects, the resistance must be minimized to avoid degradation of global interconnect performance. Furthermore, detailed 3-D electrothermal simulations indicate that Joule heating and thermal contact resistance between CNTs and metal can be a major bottleneck in extracting the maximum thermal performance from ballistic CNT bundle vias. From a processing perspective, we show that the applicability of MWCNT vias, which are currently being fabricated, is severely limited by their large thermal and electrical resistance. For SWCNT- and DWCNT-based vias, small-diameter CNTs with dense packing as well as good thermal and electrical contact between CNT and metal are needed.

Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits

This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chips power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

Management of electrothermal (ET) issues arising due to power dissipation both at the micro- and macro- scale is central to the development of future generation microprocessors, integrated networks, and other highly integrated circuits and systems. This paper provides a broad overview of various ET effects in nanoscale VLSI and highlight both technology and design choices that are thermally-aware. First, effects at the micro scale - in interconnects and devices and their implications for performance, reliability and design are discussed. Next, macro scale-circuit and system level issues including substrate temperature gradients as well as strong ET couplings between supply voltage, frequency, power dissipation and junction temperature in leakage dominant technologies are outlined. A recently developed system level ET analysis methodology and tool that comprehends ET couplings in a self-consistent manner and can generate accurate thermal profile of the substrate is summarized. The application of the ET-tool is demonstrated in a number of areas from power-performance-cooling cost tradeoff analysis to circuit optimization, full-chip leakage estimation, and temperature/reliability aware design space generation. Implications of chip cooling for nanometer scale bulk and SOI based CMOS technologies are also discussed. The ET analysis tool is also shown to be useful for hot-spot management. The paper ends with a brief discussion of electrothermal issues in emerging 3D ICs and highlights the advantages of employing hybrid carbon nanotube-Cu interconnects in both 2D and 3D designs