Roberto Suaya

Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs

This paper introduces the first comprehensive and accurate compact resistance-inductance-capacitance-conductance (RLCG ) model for through-silicon vias (TSVs) in 3-D ICs valid from low- to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy currents in the silicon substrate. The model is verified against electrostatic measurements as well as a commercial full-wave electromagnetic simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a slight modification (making the effective conductivity complex) is made. Various geometries (as per the International Technology Roadmap for Semiconductors) and prospective materials (Cu, W, and single-walled/multiwalled CNTs) are evaluated, and a comparative performance analysis is presented. It is shown that CNT-bundle-based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to the reduced skin effect in CNT bundle structures. On the other hand, the performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, it is shown that CNTs provide an improved heat dissipation path due to their much higher thermal conductivity. In addition, the improved mechanical robustness and thermal stability of CNTs also favor their selection as TSV materials in emerging 3-D ICs.

Compact AC modeling and analysis of Cu, W, and CNT based through-silicon vias (TSVs) in 3-D ICs

This paper introduces the first accurate compact RLCG model for through-silicon vias (TSVs) in 3-D ICs valid for both low- and high-frequency regime, with consideration of MOS effect in silicon, AC conduction in silicon, skin effect in TSV metal and eddy currents in silicon substrate. The model is verified against a commercial full-wave electromagnetic (EM) simulation tool and subsequently employed for various performance (delay) analyses. The compact model is also applicable to TSVs made of carbon nanotube (CNT) bundles, once a small modification (making the effective resistivity complex) is made. Various geometries (as per the ITRS) and prospective materials (Cu, W, and Single-Walled (SW)/Multi-Walled (MW) -CNTs) are evaluated and comparative performance analysis is presented. It is shown that MWCNT bundle based TSVs can offer smaller or comparable high-frequency resistance than those of other materials due to reduced skin-effect in CNT bundle structures. On the other hand, performance (delay) analysis indicates that the performance differences among different TSV materials are rather small. However, since CNTs have other benefits over Cu and W (e.g., much higher thermal conductivity and better robustness and thermal stability), they could be the material of choice for TSVs in emerging 3-D ICs.

Compact Modeling and Analysis of Through-Si-Via-Induced Electrical Noise Coupling in Three-Dimensional ICs

Through-silicon vias (TSVs) in 3-D integrated circuits (ICs), which are used for connecting different active layers, introduce an important source of coupling noise arising from electrical coupling between TSVs and the active regions. This paper, for the first time, presents compact models based on a fully analytical approach for the electrical coupling from a TSV to the active regions for a comprehensive set of 3-D IC substrate technologies including those with and without the high-conductivity buried layer in dual-well bulk CMOS technology in the presence of VDD/VSS rails. The models can be used during design validation of emerging 3-D ICs. The compact physical models are verified against full-wave electromagnetic (EM) simulations. A comparative analysis of the magnitude of the EM coupling noise for different 3-D technology scenarios, including both dual-well bulk CMOS and partially depleted silicon-on-insulator, is also presented. The compact models presented for dual-well bulk CMOS are subsequently employed for estimating the stay-away radius (safe distance) from the center of the TSVs to the active regions to minimize the impact of such coupling noise. In order to highlight the significance of the TSV to active-region EM coupling noise, a comparison is also made with the white noise in the active region and the flicker noise from the interface between the TSV oxide and silicon.

Exponential Data Fitting and its Applications

Type Ia supernova light curves are characterized by a rapid rise from zero luminosity to a peak value, followed by a slower quasi-exponential decline. The rise and peak last for a few days, while the decline persists for many months. It is widely believed that the decline is powered by the radioactive decay chain 56Ni → 56Co → 56Fe, but the rates of decline in luminosity do not exactly match the decay rates of Ni and Co. In 1976, Rust, Leventhal, and McCall [19] presented evidence that the declining part of the light curve is well modelled by a linear combination of two exponentials whose decay rates were proportional to, but not exactly equal to, the decay rates for Ni and Co. The proposed reason for the lack of agreement between the rates was that the radioactive decays take place in the interior of a white dwarf star, at densities much higher than any encountered in a terrestrial environment, and that these higher densities accelerate the two decays by the same factor. This paper revisits this model, demonstrating that a variant of it provides excellent fits to observed luminosity data from 6 supernovae.

Transmission line design of clock trees

We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations proposed by Davis and Meindl. We make appropriate modifications due to finite rise time. They affect the delay calculation and hypothesis pertaining the constancy of the electromagnetic parameters. We study these effects in detail. To find the domain of physical variables where transmission line behavior is feasible, we pose the problem as a nonlinear minimization problem in a space spanned by two continuous variables, with four parameters. From the resulting solutions and employing monotonicity properties of the functional we extract regimes of validity. These regimes of validity happen to be commensurate with what is reachable and doable with todays leading technologies. We complete this study with a qualitative analysis of driver insertion in the presence of transmission lines. The resulting configurations are suitable for the development of an improved clock design discipline.

A Fully Analytical Model for the Series Impedance of Through-Silicon Vias With Consideration of Substrate Effects and Coupling With Horizontal Interconnects

This paper introduces a fully analytical and physical model capable of extracting high-frequency series impedance of through-silicon vias (TSVs) in 3-D integrated chips with consideration of the eddy currents in the surrounding Si substrate and coupling with horizontal interconnects. The model employs the vertical-to-vertical and horizontal-to-vertical 3D vector potential Greens function in layered media and is concise and sufficiently accurate in the entire range of interest for both the frequency and the center-to-center distance between TSVs. Along with the series impedances between horizontal wires, which are extracted from the discrete complex image method, as well as the TSV and horizontal wire capacitance values, the total loop impedance can be obtained. Our approach is verified against a full-wave finite- element-method electromagnetic solver High Frequency Structure Simulator, and it shows good accuracy (<; 7% error) in the entire frequency range examined (up to 100 GHz). Given the fact that the formulated TSV series impedance model is purely analytical, the model could be efficiently used for system-level interconnect impedance extraction in emerging 3-D integrated systems.

Two-dimensional IC layout compaction based on topological design rule checking

An effective approach to two-dimensional compaction of VLSI circuit layouts is discussed. Active devices are described in terms of circular primitives called bubbles. The wires are treated topologically in that no geometric representation is used for them during compaction. This avoids expensive geometrical manipulations of the wires. Cells are compacted by moving bubbles one at a time along design rule preserving paths so as to minimize a cost function directly related to the size of the cell. Geometrical realizations of the wires are reconstructed at the end of the compaction process. The resulting routing has minimum wire length for each wire. >

An improved long distance treatment for mutual inductance

This paper examines the controversy between two approaches to inductance extraction: loop versus partial treatments for integrated circuit applications. We advocate the first one, and explicitly show that the alternative demands monopole-like magnetic configurations as well as dense inductance matrices. We argue that the uncertainties in the loop inductance treatment associated with possibly unknown return paths are in fact negligible for frequencies where inductance effects are important. Within the loop formulation, we develop an efficient way of computing mutual inductances between loops in terms of the field generated by a magnetic dipole. We derive easily computable analytical formulas. On numerical simulations, this dipole approximation (DA) shows good accuracy when compared to FastHenry, down to distances smaller than 30 /spl mu/m for 90-nm lithography. The DA leads naturally to selection rules for discarding the coupling for certain geometrical configurations, an experimentally verifiable prediction.

Optimal design of clock trees for multigigahertz applications

With the onset of gigahertz frequencies on clocked digital systems, inductance effects become significant. We investigate appropriate regimes where signal propagation on an IC can be characterized as resulting from transmission line (TL) behavior. The signals propagate at a speed in the proximity of the speed of light in the medium. Our starting points are exact solutions in the time domain to the TL equations. A methodology to evaluate the feasible domains of physical and electrical variables that permit TL propagation is given. We develop fast and accurate computational methods for inductance and capacitance calculations. A general expression of the time delay in the presence of finite rise time and finite load capacitance for TL propagation is derived. We analyze a clock-synthesis method based on sandwiched balanced H-trees consistent with TL propagation. We find the feasible physical domains by solving iteratively two nonlinear equations in a space spanned by two continuous variables, with four parameters. To further assert its applicability we remove common assumptions such as the constancy of the electromagnetic parameters, zero rise time, and load capacitance. The spectrum of configurations is satisfactory at 130 nm and scales well into the 45-nm generation.

Compact modeling and analysis of coupling noise induced by through-Si-vias in 3-D ICs

Through-silicon vias (TSVs) in 3-D ICs, which are used for connecting different active layers, introduce an important source of coupling noise arising from electromagnetic (EM) coupling between TSVs and the active regions. This work, for the first time, presents compact models based on fully analytical approach for the EM coupling from a TSV to the active regions for a comprehensive set of 3-D IC substrate technologies including those with and without the high conductivity buried layer in dual-well bulk CMOS. The models can be used during design validation of emerging 3-D ICs. The compact physical models are verified against full-wave EM simulations. A comparative analysis of the magnitude of the EM-coupling noise for different 3-D technology scenarios, including both dual-well bulk CMOS and partially-depleted silicon-on-insulator (SOI) is also presented. The compact models presented for dual-well bulk CMOS are subsequently employed for estimating the stay-away radius (safe distance) from the center of the TSVs to the active regions to minimize the impact of such coupling noise.