Nazar Abbas Saqib

A parallel architecture for fast computation of elliptic curve scalar multiplication over GF(2/sup m/)

Summary form only given. We present a generic parallel architecture for fast elliptic curve scalar multiplication over binary extension fields. We show how the parallel strategy followed in this work leads to high performance designs. We also implemented the proposed architecture on reconfigurable hardware devices where the predicted expeditious performance figures were actually obtained. The results achieved show that our proposed design is able to compute GF(2/sup 191/) elliptic curve scalar multiplication operations in 56.44 /spl mu/Secs.

A fast parallel implementation of elliptic curve point multiplication over GF(2m)

Abstract A fast parallel architecture for the implementation of elliptic curve scalar multiplication over binary fields is presented. The proposed architecture is implemented on a single-chip FPGA device using parallel strategies that trades area requirements for timing performance. The results achieved show that our proposed design is able to compute GF(2191) elliptic curve scalar multiplication operations in 63 μs.

A fast implementation of multiplicative inversion over GF(2/sup m/)

In this paper, an efficient architecture for multiplicative inversion in GF(2/sup m/) using addition chains is presented. The approach followed was based on the Itoh-Tsujii algorithm targeting a fast implementation on reconfigurable hardware devices. We give the design details of the proposed architecture whose main building blocks are a field multi-squarer block, a field polynomial multiplier and a BRAM two-port memory. Our design is able to compute multiplicative inversion in GF(2/sup 193/) in about 1.33/spl mu/S using only 27 clock cycles.

AES algorithm implementation - an efficient approach for sequential and pipeline architectures

We present an efficient implementation of the Rijndael cryptographic algorithm on FPGAs, which is a new advanced encryption standard (AES). The implementation of AES has been carried out in both sequential and pipeline architectures and we are able to compare the results as an area time trade-off. In sequential architecture, the design occupies 2744 CLB slices and achieves a throughput of 258.5 Mbit/s and there is no use of extra memory resources like FPGA BRAMS. On the other hand, our pipeline design occupies a total of 2136 CLB slices and achieved a throughput of 2868 Mbit/s. Both designs were realized on the VirtexE family of devices (XCV812). The performance figures achieved by our implementations are not only efficient in terms of throughput but also areas occupied by them are among the most economical reported to date.

On Detection and Prevention of Clickjacking Attack for OSNs

Click jacking attacks are the emerging threats to websites, especially to online social networks (OSNs). In this paper, we describe some new attacks to online websites. The new Click jacking attacks cause serious damage to users by stealing their personal credentials or by sharing their personal information on social networks bringing moral degradation to them. The attacker applications are hidden behind the sensitive user interface to steal the clicks of the user and use them for the illegal purposes. To detect and prevent Click jacking attacks, we propose a browser-based solution referred to as Cursor Spoofing and Click jacking Prevention (CSCP). CSCP ensures protection Cursor spoofing attack with high effectiveness and also the Like jacking attacks, other variation of Click jacking attacks which associate malicious code to Facebook Like buttons. We have conducted our studies on 442 participants to evaluate the effectiveness of our attacks and also defenses. Results show that our attack success rate falls between 76% and 78%.

Selective HARQ Transceiver Design for OFDM System

We present a novel selective Hybrid Automatic Repeat reQuest (HARQ) based transceiver design for orthogonal frequency division multiplexing (OFDM) system. The proposed method is bandwidth efficient and has lower complexity as compared to conventional HARQ method adopted by communication standards such as long-term evolution (LTE). Our transceiver design introduces an additional retransmission layer at OFDM modulation level, which is independent of conventional HARQ methods. Instead of calculating computationally expensive soft information and applying forward error correction (FEC) on the soft information, receiver requests retransmission of information symbols corresponding to the subcarriers that have signal-to-noise ratio (SNR) below a set threshold at modulation level. We also provide criteria for selective retransmission and throughput analysis with new selective retransmission approach. We demonstrate that with limited feedback at modulation layer level, the proposed method enhances throughput of the system in all SNR regimes. The proposed selective HARQ method provides great flexibility for an application to optimize throughput based on its bit error rate (BER) requirement.

A reconfigurable processor for high speed point multiplication in elliptic curves

This paper presents a generic architecture for the computation of elliptic curve scalar multiplication over binary extension fields. In order to optimise the performance as much as we could, we designed a parallelised version of the well-known Montgomery point multiplication algorithm implemented on a reconfigurable hardware platform (Xilinx XCV3200). The proposed architecture allows the computation of the main building blocks required by the Montgomery algorithm in an efficient manner. The results achieved show that our proposed design is able to compute GF(2191) elliptic curve scalar multiplication operations in just 22 clock cycles at a frequency of about 10 MHz. Moreover, our structure is able to obtain a scalar multiplication in less than 60 µSecs.

A survey of multicast routing protocols for vehicular ad hoc networks

Vehicular Ad Hoc Networks (VANETs) are autonomous and self-configurable wireless ad hoc networks and considered as a subset of Mobile Ad Hoc Networks (MANETs). MANET is composed of self-organizing mobile nodes which communicate through a wireless link without any network infrastructure. A VANET uses vehicles as mobile nodes for creating a network within a range of 100 to 1000 meters. VANET is developed for improving road safety and for providing the latest services of intelligent transport system (ITS). The development and designing of efficient, self-organizing, and reliable VANET are a challenge because the nodes mobility is highly dynamic which results in frequent network disconnections and partitioning. VANET protocols reduce the power consumption, transmission overhead, and network partitioning successfully by using multicast routing schemes. In multicasting, the messages are sent to multiple specified nodes from a single source. The novel aspect of this paper is that it categorizes all VANET multicast routing protocols into geocast and cluster-based routing. Moreover, the performance of all protocols is analyzed by comparing their routing techniques and approaches.

Covert channel detection: A survey based analysis

Secret communication via network has always been an area of interest for many. It has not only attracted the trusted parties to communicate with each other secretly but has also attracted the hackers/attackers to find ways to discover and leak the information and use the network in a manner that violate security policies. Steganography and covert channels are most widely used approaches for secret communication. Number of detecting techniques has been proposed for steganography and covert channel detection. This paper covers detecting techniques of covert channel only as the covert channel is a modern way of leaking information and it is difficult to detect such channels. Covert channel falls into two categories: storage covert channel and timing covert channel. Storage covert channel is created by manipulating the header fields of packets whereas timing covert channel is created by timing of event i.e. arrival pattern of packets. In this paper different techniques for detecting storage and timing covert has been surveyed and analysis of these techniques is done.

A parallel architecture for computing scalar multiplication on Hessian elliptic curves

A parallel architecture for the computation of Hessian elliptic curve scalar multiplication over binary fields is presented. The architecture was designed as general as possible trying to make no assumptions about the specific hardware platform to be used by the designers. The idea of using parallel strategies was considered in every design stage and implemented as much as hardware resources allowed us to do it so. The design results reported allow us to compute GF(2/sup 191/) elliptic curve scalar multiplication operations in about 114.7/spl mu/ Secs.