Nazrul Anuar

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to V dd . It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 ㎒. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Two phase clocked adiabatic static CMOS logic

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-flipflop are 77.2% and 55.5% less than that in a static CMOS at transition frequencies of 10–100 MHz respectively.

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

This paper presents the simulation results of a 4×4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 µm standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies of 1 to 100 MHz, 4×4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) employing 2PASCL circuit technology. Energy dissipation in the 2PASCL RCA is 71.3% lesser than that in a static CMOS RCA at transition frequencies of 10-100 MHz.

Fundamental logics based on two phase clocked adiabatic static CMOS logic

This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 µm CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. From the simulation results, we find that 2PASCL inverter logic can save up to 97% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 10 to 100 MHz. Further, the power dissipation is the lowest when compared with other proposed simple adiabatic logic inverters. 2PASCL also achieves the highest fan-out performance. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

4-bit ripple carry adder using two phase clocked adiabatic static CMOS logic

This paper demonstrates the low energy operation of 4-bit ripple carry adder (RCA) employing two phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. We evaluate NOT, NAND, XOR and NOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 -m CTX CMOS technology. For NOT circuit, analytical and simulation values are compared. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. From the simulation results, we find that 4-bit 2PASCL RCA can save an average of 71.3% of dissipated energy as compared to that with a static 4-bit CMOS RCA at transition frequencies of 10 to 100 MHz. The results indicates that 2PASCL technology can be advantageously applied to low-power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

XOR evaluation for 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier

This paper evaluates four designs of XOR employing our previously presented two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for the 4×4-bit array 2PASCL multiplier. From our simulation results, at transition frequencies of 1 to 100 MHz, the 4×4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS.

On chip LC resonator circuit using an active inductor for adiabatic logic

In this paper, we propose a LC resonator circuit using Haras active inductor for adiabatic logic. The proposed circuit consists of four MOS-transistors Colpitts oscillator and an active inductor. This circuit require no inductor and can be produced two-phase sinusoidal clocking. From the simulation results, we show that the proposed circuit was operated as a 10 MHz, 3 V peak-to-peak LC resonant oscillator.