Neil Steiner

Torc: towards an open-source tool flow

We present and describe Torc - (Tools for Open Reconfigurable Computing) - an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://torc.isi.edu. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration. The Torc infrastructure can (1) read, write, and manipulate generic netlists - currently EDIF, (2) read, write, and manipulate physical netlists - currently XDL, and indirectly NCD, (3) provide exhaustive wiring and logic information for commercial devices, and (4) read, write, and manipulate bitstream packets (but not configuration frame contents). Torc furthermore provides routing and unpacking tools for full or partial designs, soon to be augmented with BLIF support, and with packing and placing tools. The architectural data for Xilinx devices is generated from non-proprietary XDLRC files, and currently supports 140 devices in 11 families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex4, Virtex5, Virtex6, Virtex6L, Spartan3E, Spartan6, and Spartan6L. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures.

Parallelizing Iris Recognition

Iris recognition is one of the most accurate biometric methods in use today. However, the iris recognition algorithms are currently implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). In this work, we present a more direct and parallel processing alternative using field-programmable gate arrays (FPGAs), offering an opportunity to increase speed and potentially alter the form factor of the resulting system. Within the means of this project, the most time-consuming operations of a modern iris recognition algorithm are deconstructed and directly parallelized. In particular, portions of iris segmentation, template creation, and template matching are parallelized on an FPGA-based system, with a demonstrated speedup of 9.6, 324, and 19 times, respectively, when compared to a state-of-the-art CPU-based version. Furthermore, the parallel algorithm on our FPGA also greatly outperforms our calculated theoretical best Intel CPU design. Finally, on a state-of-the-art FPGA, we conclude that a full implementation of a very fast iris recognition algorithm is more than feasible, providing a potential small form-factor solution.

JHDLBits: The Merging of Two Worlds

This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits with the high-level structural circuit design of JHDL. Furthermore, the JHDLBits flow provides greater control of resource manipulation, placement, and routing, and gives researchers a “sandbox” to explore advanced interactions with FPGA bitstreams. This paper presents the overall architecture of the open-source JHDLBits project. Details are provided on how the core components – JHDL, JBits3 for Virtex-II, and the ADB connectivity database – are linked together to provide a cohesive design environment.

Open-Source Bitstream Generation

This work presents an open-source bitstream generation tool for Torc. Bitstream generation has traditionally been the single part of the FPGA design flow that could not be openly reproduced, but our novel approach enables this without reverse-engineering or violating End-User License Agreement terms. We begin by creating a library of “micro-bitstreams” which constitute a collection of primitives at a granularity of our choosing. These primitives can then be combined to create larger designs, or portions thereof, with simple merging operations. Our effort is motivated by a desire to resume earlier work on embedded bitstream generation and autonomous hardware. This is not feasible with Xilinx bitgen because there is no reasonable way to run an x86 binary with complex library and data dependencies on most embedded systems. Initial support is limited to the Virtex5, but we intend to extend this to other Xilinx architectures. We are able to support nearly all routing resources in the device, as well as the most common logic resources.

Hardware autonomy and space systems

Autonomous capability in space systems is rapidly becoming a necessity for continued research and exploration. While these systems have traditionally behaved as passive observers, their remoteness and unique access to unexplored environments will likely result in future systems that behave more like active agents employed on our behalf. We may still determine the larger mission goals and priorities, but the systems themselves will be better able to direct their own movement, schedule, and operation.

An alternate wire database for Xilinx FPGAs

This paper presents ADB, an alternate wire database, suitable for routing, tracing, and browsing in Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs. While mainstream design flows and place-and-route tools make good use of available routing resources, they often do so at the cost of comparatively large processing times. An alternative scheme is to modify or generate configuration bitstreams directly, in order to achieve more dynamic designs and to reduce processing times and memory footprints. ADB includes a complete set of compact wire databases for the indicated families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface. These wire databases can also be used in standalone mode to facilitate routing research in situations where real device data might not normally be available.

HwPMI: an extensible performance monitoring infrastructure for improving hardware design and productivity on FPGAs

Designing hardware cores for FPGAs can quickly become a complicated task, difficult even for experienced engineers. With the addition of more sophisticated development tools and maturing high-level language-to-gates techniques, designs can be rapidly assembled; however, when the design is evaluated on the FPGA, the performance may not be what was expected. Therefore, an engineer may need to augment the design to include performance monitors to better understand the bottlenecks in the system or to aid in the debugging of the design. Unfortunately, identifying what to monitor and adding the infrastructure to retrieve the monitored data can be a challenging and time-consuming task. Our work alleviates this effort. We present the Hardware Performance Monitoring Infrastructure (HwPMI), which includes a collection of software tools and hardware cores that can be used to profile the current design, recommend and insert performance monitors directly into the HDL or netlist, and retrieve the monitored data with minimal invasiveness to the design. Three applications are used to demonstrate and evaluate HwPMIs capabilities. The results are highly encouraging as the infrastructure adds numerous capabilities while requiring minimal effort by the designer and low resource overhead to the existing design.

Hardware-software interaction: preliminary observations

As computational devices continue to advance, there are reasons to examine their foundations a little more deeply, and to ask whether there may not be something more to be found. The fundamental manner in which hardware and software interact is poorly understood, and yet there is little indication in the literature that this is being discussed or explored. In spite of our technological achievements, we are at a loss to precisely define the boundaries between hardware and software, and to describe the nature of their interface. This paper aims to raise some of the major issues and questions, to propose a hardware-information duality, and to suggest directions in which further research might be pursued.

Hardware based segmentation in iris recognition and authentication systems

Iris recognition algorithms depend on image processing techniques for proper segmentation of the iris. In the Ridge Energy Direction (RED) iris recognition algorithm, the initial step in the segmentation process searches for the pupil by thresholding and using binary morphology functions to rectify artifacts obfuscating the pupil. These functions take substantial processing time in software on the order of a few hundred million operations. Alternatively, a hardware version of the binary morphology functions is implemented to assist in the segmentation process. The hardware binary morphology functions have negligible hardware footprint and power consumption while achieving speed up of 200 times compared to the original software functions.