Neil Weste

Virtual Grid Symbolic Layout

Free form or “stick” type symbolic layout provides a means of simplifying the design of IC subcircuits. To successfully utilize this style of layout, a complete design approach and the necessary tools to support this methodology are required. In particular, one of the requirements of such a design method is the ability to “compact” the loosely specified topology to create a set of valid mask data. This paper presents a new compaction strategy which uses the concept of a virtual grid. The compaction algorithm using the virtual grid is both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout. In addition to the compaction algorithm, methods used to create large building blocks will be described. The work described here is part of a complete symbolic layout system called MULGA which is written in the C programming language and resides on the UNIX operating system.

VLSI for OFDM

This article discusses the VLSI implications of high-speed coded orthogonal frequency-division multiplexing modulation. This is achieved by looking at practical examples of the computational blocks that constitute a COFDM modem and then examining examples of COFDM chips.

A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback

A 500 MHz op-amp-RC filter in a 0.18 /spl mu/m CMOS process achieves an integrator signal swing of 1.73 V/sub pp/ for -40 dB THD and thermal noise of 18 nV//spl radic/Hz. A three-stage op-amp with two feed-forward paths and common-mode feedback local to each stage is used. The op-amp features 8 GHz unity-gain frequency and 40 dB gain at 500 MHz.

A single chip PHY COFDM modem for IEEE 802.11a with integrated ADCs and DACs

This chip, fabricated in a 0.25/spl mu/m 5M1P CMOS process with 3.7M transistors, implements a fully-compliant IEEE 802.11a PHY modem. The IEEE 802.11a standard provides for wireless local area networks (WLANs) with a physical layer based on coded orthogonal frequency domain multiplexing (COFDM) modulation, delivering data rates up to 54Mb/s, operating in the 5GHz UNII frequency bands. The article outlines the role of a physical layer (PHY) modem in such a WLAN system. The PHY modem lies between a medium access controller (MAC) and a 5GHz radio transceiver, and is responsible for demodulating and modulating a baseband analog signal with data from the MAC. In 802.11a the baseband signal is a 64 subcarrier COFDM signal with BPSK, QPSK, QAM16 or QAM64 modulated subcarriers.

Array configurations for dynamic time warping

In a previous paper an array architecture was revealed for real-time dynamic time warping. An integrated processor was designed and built for use in such an array. This paper discusses reduced arrays which allow a continuum of tradeoffs between speed and circuit complexity. Reduced arrays permit design of fixed-size systems for problems which are unbounded in size.

A high speed array computer for dynamic time warping

Dynamic time warping is an established technique for time alignment and comparison of speech segments in speech recognition. This paper describes a CMOS integrated array processor for computing the dynamic time warp algorithm. It allows many popular variations including LPC and frequency domain representations of speech. High speed is obtained by extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic application using 40 nine-component LPC vectors per word permits 10,000 word comparisons per second or, equivalently, real time recognition of a 10,000 word vocabulary.

60GHz Radios: Enabling Next-Generation Wireless Applications

Up to 7 GHz of continuous bandwidth centred around 60 GHz has been allocated worldwide for license free wireless communications. Highly attenuated due to oxygen absorption and small in wavelength, this band is ideal for extremely high data rate wireless data applications. These include numerous WPAN/WLAN applications such as home multimedia streaming. Traditional RF circuits used in this band are based on expensive compound semiconductor technologies. However for viable consumer applications, alternatives must be found. SiGe and CMOS based circuits are showing promise for enabling this technology at a price within reach of the consumer. This paper summarises a joint project aimed at developing high rate consumer level mm-wave wireless data systems. In particular, results to date in our RF design efforts are summarised.

A systolic processing element for speech recognition

An integrated 16b CMOS processor designed for systolic array processing, with programmable processors, capable of performing the pattern matching required for speech recognition of up to 25,000 words per second will be described.

Real time animation playback on a frame store display system

A frame store display station capable of generating real time animation effects using filled polygonal shapes is described. The system consists of a host microcomputer, a high performance frame store display controller and a microprogrammed graphic command interpreter. Real time performance is attained using a combination of software, hardware and a systems approach. The display station can be used to interactively test and view simple animation sequences. Some proposals for further increasing performance are discussed.

ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective

This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation results indicate two or more ADC bits are required for reliable data reception in the presence of strong interference and intermodulation distortion. In addition to BER performance, power consumption of different hardware configurations is also evaluated to form the cost function for evaluating design choices. The combined power and performance analysis indicates that starting with one-bit ADC resolutions, a substantial gain in reliability can be attained by increasing ADC resolution to two-bits or more. When the ADC resolution improves beyond three bits, front-end linearization achieves similar BER improvements to increasing the ADC accuracy, at a fraction of the power cost. As a result, linear front-end designs become significant only when high precision ADCs are utilized.