Nejmeddine Jouida

Comparative Study between Continuous-Time Real and Quadrature Bandpass Delta Sigma Modulator for Multistandard Radio Receiver

This paper presents a continuous-time quadrature bandpass delta sigma modulator which offers significant theoretical and practical performance advantages over the alternative of a pair of traditional bandpass DeltaSigma modulator. The comparative study between the two types of modulator, real and quadrature, for multistandard radio receiver is based on the low-IF receiver architecture, which, with modern quadrature image reject mixers and strategic IF placement, offers a viable solution for realizing digital, monolithic receivers. 10th order real, 3rd and 5th order quadrature bandpass modulator are designed and discussed for dual standard Bluetooth and WiFi.

Built-in Filtering for Out-of-Channel Interferers in Continuous-Time Quadrature Bandpass Delta Sigma Modulators

This paper presents the design of implicit filtering for out-of-channel interferers in continuous-time (CT) quadrature bandpass (QBP) ΔΣ modulator using a differentiated signal-transfer-function (STF). Comparative study between possible ΔΣ modulator loop filter structures is addressed to better cope with the best implementation. The Fifth-order CT QBP ΔΣ modulator planned for the WiFi adjacent channel blockers requirements, illustrates clearly the totally elimination of interferers and the correctly signal process. This led to remove the baseband filter and PGA at the price of a very challenging ADC with merged-in cited functionalities. So, less analog components, low power consumption and high performance for the low-IF receiver.

Continuous-Time Complex Bandpass Modulator: Key Component for Highly Digitized Receiver

This paper presents a highly digitized receiver for a single chip digital radio receiver. The RF front-end has been based on a low-IF architecture and does not require any variable gain or filtering blocks. The full dynamic range of the low-IF signals is converted into the digital domain by a low-power high-resolution continuous-time (CT) DeltaSigma analog-to-digital converter (ADC). The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. Fifth order CT complex bandpass (BP) DeltaSigma modulator was planned for duo standard, Bluetooth and WiFi to illustrate the receiver multistandard effectiveness. The quadrature modulator digitizes complex analog I/Q input signals at 5 MHz intermediate frequency and operates with a clock frequency of 200 MHz. The modulator achieves a peak SNR of 87.48 dB at 10 MHz bandwidth for IEEE 802.11b and 96.76 dB at 1 MHz bandwidth for Bluetooth.

Top-down design process for continuous-time delta sigma modulators

This paper presents a top-down design process for continuous-time (CT) DeltaSigma modulator. Design strategy is illustrated through a fifth-order modulator designed for Bluetooth, WiFi and WiMAX which exemplify clearly the design methodology. Numerous simulations make obvious that the formulate strategy can be successfully applied to practical problems.

VHDL-AMS modeling of non-idealites effects in Continuous-time quadrature bandpass ΔΣ modulator

This paper presents an approach of behavioral modeling, simulation, and design of Continuous-time (CT) quadrature bandpass (QBP) ΔΣ modulator using VHDL-AMS language. A set of specific behavioral models taking into account non-idealities effects such excess loop delay and jitter are developed. Numerous behavioral simulation of a fifth-order CT QBP ΔΣM illustrates and quantifies the impact of these non-idealities effects.

Mixed-signal design methodology for continuous-time quadrature bandpass ΔΣ modulator

Continuous-time (CT) quadrature bandpass (QBP) delta-sigma (ΔΣ) modulator is already in itself a mixed-signal system. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. This paper presents an efficient top-down methodology for mixed-signal design. We report the design process from the system-level down to gate/transistor-level; modeling and simulation are applied to the ΔΣ modulator. We have verified the robustness and effectiveness of our approach which resulted in shorter design process cycles and higher rates of success.

Multistandard digital channel selection using decimation filtering for ΔΣ modulator

This paper presents a new methodologie of a decimator filter design in a multistandard receiver architecture for WiFi and Bluetooth. This filter must satisfy the specifications of a fifth DeltaSigma complex bandpass modulator which operates at a sample rate of 160 MHz. The function of the decimator filter is to make the channel digital selection for duo standards WiFi (IEEE 802.11g) and Bluetooth (IEEE 802.15.1). In other hand, a digital down converter is necessary to make a frequency translation in baseband.

Design strategy for high order continuous-time ΔΣ modulator for multistandard receiver

This paper presents a systematic technique for designing high order stable continuous-time (CT) delta-sigma modulator (ΔΣM) for multistandard receiver. The proposed design methodology permits the synthesis of 78M employing continuous-time integrators and resonators from discrete-time topologies. 5th and 10th order respectively Low Pass (LP) and Band Pass (BP) ΔΣM examples are given to illustrate the presented approach. The modulators are designed for GSM/UMTS/WLAN receiver and achieve, respectively, a dynamic range (DR) more than 98/70/40 dB.