Nenad Cetic

Voice control system with advanced recognition

This paper explains the process of realization of voice control system based on the cloud processing. The aim is the feasibility study of system based on integration with Google STT API (Speech to text, recognition and speech synthesis) for different platforms. This approach introduces advanced recognition module that operate on text level. Improving recognition leads to further improvement of the overall system behavior.

Estimating parallelism of Transactional Memory programs

Transactional Memory (TM), a promising concurrency control mechanism that enables easier and more productive parallel/distributed programming, become a standard part of the latest multicores rolled out by IBM, Intel, AMD, and other IC manufacturers. Many TM aspects have been intensively researched, e.g. semantics of various possible implementations, TM safety and liveness properties, and TM performance. Some researchers suggested some novel measures for the amount of concurrency in TM programs. Alternatively, we in this paper propose an approach to analysis of TM programs by using a well-established methodology, which is based on modeling programs as DAGs, and calculating their work, span, parallelism, and speedup. In the paper we present an approach to application of this methodology in order to calculate the parallelism of a typical TM program for processing a group of transactions on a set of bank accounts. As a result of this approach we established some simple theorems that may be used for analysis of a broader class of TM programs.

Communication interface libraries as an extension to the debugging framework for DSP applications

In this paper we present an approach for creating communication interface libraries using remote procedure call technique within client-server based debugger. Presented approach tries to prove the simplicity of porting the libraries to different programming or scripting languages, which greatly improves portability and extensibility of the framework, and facilitates the user experience. By using remote procedure call technique and an interface compiler, we have successfully created libraries for two different programming languages C++ and Python.

Software for automatic control of laboratory analysis

Inspection of physical and chemical substance characteristics makes an important part of product realization processes for many industrial systems. These processes require testing of dozens or hundreds of samples daily, in order to determine the value of the material characteristics and compare it with the established quality limits. Systematization and application of laboratory tests results would be poor quality without the proper computer support. This paper presents software intended for laboratories that monitor production processes.

HTTP server for control of home appliances based on XMOS platform

Implementation of a smart house control system is given in this paper. The management over the network involves the use of special-purpose devices based on a microcontroller produced by company XMOS and specific software developed. This system provides control of household appliances through mobile devices (phones, iPhone / Android devices) or any other device that has a Web browser.

A Retargetable C Compiler for Embedded Systems

With the expansion of the market of available embedded platforms the variety of target architectures is rapidly increasing. Therefore the need for retarget able software development tools has never been greater. The C compiler, probably the most significant development tool for embedded systems, is required to be quickly and easily adaptable for new architectures. This paper describes one such generic C compiler which has been adapted for Crystal 32-bit and MIPS 32-bit as two different target platforms. The aim of this paper is to prove that the compiler has modifiable infrastructure and can be easily adapted to support new architectures, as well as to improve the compiler in terms of extending this capability. The compiler has been tested for correctness for both architectures. For Crystal 32-bit platform quality testing has also been performed and all test results showed remarkable results. On the other hand, for MIPS 32-bit architecture, for which full compiler support is still an ongoing process, correctness tests were performed with exceptions of C language aspects which are not commonly used in embedded system applications. The analyses of these tests showed convincing results for embedded domain and promising results for reaching full MIPS 32-bit support.

A Run-Time Library for Parallel Processing on a Multi-core DSP

Future of the computer based systems resides in the multi-core and many-core architectures. Thanks to availability of different multi-core processors, many parallelization tools and techniques emerged. However, majority of them rely on the shared memory architecture model, where data to multiple core processors is simply accessible. In this paper we present a simple hardware abstraction that targets features of a multi-core DSP processor with distributed memory architecture, aiming support for program parallelization. Both manual and automatic code parallelization approaches can use library routines described in this paper. By validating performance of multiple manually created test cases we demonstrate capabilities of presented approach. Performance is estimated by measuring time necessary for DMA data transfer between the cores using GPIO pins attached to the DSP. In addition, earlier developed C code parallelization technique for the same DSP is extended to use this library providing full working solution verified on real hardware.

An approach to instruction set compiled simulator development based on a target processor C compiler back-end design

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge related to compilers and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented showing that this approach has great potential.

An Approach to Instruction Set Compiled Simulator Development Based on a Target Processor C Compiler Back-End Design

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to try to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge from that field of work and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented proving that this approach has a great potential.

A C compiler based methodology for implementing audio DSP applications on a class of embedded systems

This paper describes a methodology for a common task of audio application implementation from the referent C code to executable image targeting an audio fixed-point mid-scale DSPs. This methodology tries to efficiently cover the gap between the referent code and the assembler code by usage of the C compiler, which supports fixed-point types defined in C language extensions for the embedded processors. By relaying on C++ classes this methodology deliveries a possibility to debug a DSP compiler ready C code in a C++ environment (e.g. Visual C++). The methodology was successfully applied to several audio applications, such as Dolby Volume, SRS TSHD, SRS VIQ, and Audyssey Dynamic EQ, and their implementation to Cirrus Logic Coyote DSP family. Experience with those applications shows that this methodology greatly shortens time to market for DSP firmware product.