Miodrag Djukic

Estimating parallelism of Transactional Memory programs

Transactional Memory (TM), a promising concurrency control mechanism that enables easier and more productive parallel/distributed programming, become a standard part of the latest multicores rolled out by IBM, Intel, AMD, and other IC manufacturers. Many TM aspects have been intensively researched, e.g. semantics of various possible implementations, TM safety and liveness properties, and TM performance. Some researchers suggested some novel measures for the amount of concurrency in TM programs. Alternatively, we in this paper propose an approach to analysis of TM programs by using a well-established methodology, which is based on modeling programs as DAGs, and calculating their work, span, parallelism, and speedup. In the paper we present an approach to application of this methodology in order to calculate the parallelism of a typical TM program for processing a group of transactions on a set of bank accounts. As a result of this approach we established some simple theorems that may be used for analysis of a broader class of TM programs.

An Approach to Parallelization of Sequential C Code

Massive parallel computing (MPC) originally appeared in the arena of multi-core processors and graphic processing units with parallel computing architecture. Nevertheless, most embedded software is still written in C, therefore C code parallelization is being subject of many ongoing R&D efforts. The most prominent approaches to parallelization of C code include Intel Cilk Plus, OpenCL, vfAnalyst, etc. The objective of this paper is to contribute to the automatic parallelization of existing sequential C code, without any source code modifications/annotations, by proposing two appropriate algorithms for parallelization, Block algorithm, and Operation based algorithm.

A Retargetable C Compiler for Embedded Systems

With the expansion of the market of available embedded platforms the variety of target architectures is rapidly increasing. Therefore the need for retarget able software development tools has never been greater. The C compiler, probably the most significant development tool for embedded systems, is required to be quickly and easily adaptable for new architectures. This paper describes one such generic C compiler which has been adapted for Crystal 32-bit and MIPS 32-bit as two different target platforms. The aim of this paper is to prove that the compiler has modifiable infrastructure and can be easily adapted to support new architectures, as well as to improve the compiler in terms of extending this capability. The compiler has been tested for correctness for both architectures. For Crystal 32-bit platform quality testing has also been performed and all test results showed remarkable results. On the other hand, for MIPS 32-bit architecture, for which full compiler support is still an ongoing process, correctness tests were performed with exceptions of C language aspects which are not commonly used in embedded system applications. The analyses of these tests showed convincing results for embedded domain and promising results for reaching full MIPS 32-bit support.

A Run-Time Library for Parallel Processing on a Multi-core DSP

Future of the computer based systems resides in the multi-core and many-core architectures. Thanks to availability of different multi-core processors, many parallelization tools and techniques emerged. However, majority of them rely on the shared memory architecture model, where data to multiple core processors is simply accessible. In this paper we present a simple hardware abstraction that targets features of a multi-core DSP processor with distributed memory architecture, aiming support for program parallelization. Both manual and automatic code parallelization approaches can use library routines described in this paper. By validating performance of multiple manually created test cases we demonstrate capabilities of presented approach. Performance is estimated by measuring time necessary for DMA data transfer between the cores using GPIO pins attached to the DSP. In addition, earlier developed C code parallelization technique for the same DSP is extended to use this library providing full working solution verified on real hardware.

An approach to instruction set compiled simulator development based on a target processor C compiler back-end design

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge related to compilers and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented showing that this approach has great potential.

A Task Tree Executor Architecture Based on Intel Threading Building Blocks

Software systems based on service oriented architecture principles, which manage critical infrastructures, are typical environments where proper parallel data processing is one of the essential goals to achieve. Designers of such systems are normally expected to optimize the system performance and/or introduce new functionalities by evolving the existing system architecture. Our aim of this paper was to optimize system performance of a SOA-based control system by evolving the architecture of the particular service component within the system, which is responsible for complex calculations on large-scale graph models, under near to real time restrictions. This service component transforms system models into task trees, which are then executed by the runtime library that is referred to as the Task Tree Executor (TTE). The goal of this paper was to introduce finer grained parallelism, thus better multicore CPU utilization, by evolving TTE architecture in such a way that novel architecture executes TTE tasks as Intel TBB tasks rather than Win32/Linux threads, which was the case for the previous TTE architecture. The experimental evaluation based on measuring time needed for TTE reliability estimation, by statistical usage tests, shows that novel TTE architecture provides the speedup of around 8 times, on average, over the previous one. Although the focus of the paper is on a particular component, of a particular system, the approach that we took should be applicable on a broader class of SOA-based systems.

An Approach to Instruction Set Compiled Simulator Development Based on a Target Processor C Compiler Back-End Design

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to try to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge from that field of work and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented proving that this approach has a great potential.

A C compiler based methodology for implementing audio DSP applications on a class of embedded systems

This paper describes a methodology for a common task of audio application implementation from the referent C code to executable image targeting an audio fixed-point mid-scale DSPs. This methodology tries to efficiently cover the gap between the referent code and the assembler code by usage of the C compiler, which supports fixed-point types defined in C language extensions for the embedded processors. By relaying on C++ classes this methodology deliveries a possibility to debug a DSP compiler ready C code in a C++ environment (e.g. Visual C++). The methodology was successfully applied to several audio applications, such as Dolby Volume, SRS TSHD, SRS VIQ, and Audyssey Dynamic EQ, and their implementation to Cirrus Logic Coyote DSP family. Experience with those applications shows that this methodology greatly shortens time to market for DSP firmware product.

Efficient adaptation and high reusability of test suites in a black box testing environment

In rapid software development environments, as software component reusability can provide significant win in productivity, the test plan readiness became essential for project success. In these conditions, when a large test plans (with high number of test cases) have to be ready and available in short time, the reusability of test cases that were already developed for specific software component is necessary.

Using a simple algorithm in SPP for audio quality improvement checkout

Smart Post-Processing (SPP) is a control algorithm for removing distortion in post-processing systems. Its most complex part is an audio quality improvement checkout routine. We have shown that even when using the simplest algorithm for this purpose results are satisfactory. On the other side it allows implementation of SPP on any commercial DSP platform, even with very restricted resources.