Neric Fong

A fully integrated multiband MIMO WLAN transceiver RFIC

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).

High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-Turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-Turn, multiple metal layers in Series) inductor.

High-performance and area-efficient stacked transformers for RF CMOS integrated circuits

A solenoid layout technique is used to increase the magnetic coupling between the coils in multi-level spiral transformers. Using this technique, transformers with the following performance are measured: (a) magnetic coupling with coupling factor k>0.95 and insertion loss s/sub 21/ better than 0.8 dB at 5 GHz; (b) self-resonant frequency f/sub res/>15 GHz with peak Q>10. The effect of high and low resistive substrates is discussed with measured results. Using this structure, the size of the transformer can be reduced from 50 to 400%.

A 40 GHz VCO with 9 to 15% tuning range in 0.13 /spl mu/m SOI CMOS

A 40 GHz fully-monolithic complementary VCO fabricated in IBM 0.13 /spl mu/m partially-depleted SOI CMOS technology is reported. The VCO operates at 1.5 V supply and draws 11.25 mW of power. The measured phase noise at 40 GHz is -109 dBc/Hz at 4 MHz offset from the carrier. At 1.5 V and 2 V V/sub DD/, the tuning range is 9% and 15% respectively, and the output power is -8 dBm and -5 dBm respectively. The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m.

A fully integrated multi-band MIMO WLAN transceiver RFIC

A multiple-input/multiple-output (MIMO) transceiver RFIC compliant with IEEE 802.11a/b/g and Japan wireless LAN (WLAN) standards is presented. The transceiver has two complete radio paths integrated on the same chip. When two chips are used in tandem to form a four-path composite beam forming (CBF) system, 15 dB of link margin improvement is obtained. The transceiver was implemented in a 47-GHz SiGe technology with 29.1-mm/sup 2/ die size. It consumes 195 mA in RX mode and 240 mA in TX mode from a 2.75-V supply.

A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS

A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The buffered output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.

24 GHz differential integrated antennas in 10 /spl Omega/-cm bulk silicon

We have demonstrated high performance, low cost, 24 GHz differential antennas on lossy 10 /spl Omega/ Si using compatible copper metallization post-processing. A gain of -8 dBi and favorable differential impedances (<50 /spl Omega/) are obtained. These antennas have strong potential for integration into VLSI technology to implement single-chip wireless systems for short range communication applications.

Highly manufacturable 40-50 GHz VCOs in a 120 nm system-on-chip SOI technology

This paper presents the design optimization and experimental results of 40-50 GHz VCOs for embedded RF integrated circuits that are widely tunable and therefore highly manufacturable. We achieved up to 15% frequency tuning range from 43.5 to 50.5 GHz and -90.2 dBc/Hz phase noise performance at 1 MHz offset from 50.1 GHz operating frequency. The total power dissipation is 15 mW at 1.8 V. The VCOs are fabricated in a 120 nm SOI technology.

On-Chip Antenna Measurements: Calibration and De-embedding Considerations

This paper presents the design and implementation of an integrated balun for testing 24 GHz on-chip differential antennas. The balun is completely characterized on lossy Si substrate for subsequent de-embedding of the antenna impedance. A simple de-embedding technique is developed and verified to extract differential antenna impedance from single-ended S-parameters. The gain of the on-chip antennas is easily estimated through a novel gain calibration technique. Finally, near to far field transformation is employed to extract full radiation patterns